Nexperia USA Inc. PSMN1R1-25YLC,115
- Part No.:
- PSMN1R1-25YLC,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SC-100, SOT-669
- Datasheet:
-
PSMN1R1-25YLC,115.pdf
- Description:
- MOSFET N-CH 25V 100A LFPAK56
- Quantity:
- Payment:

- Shipping:

Inventory:3,496
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PSMN1R1-25YLC from Nexperia is a logic-level enhancement-mode N-channel MOSFET in LFPAK (SOT669) package, optimized for 4.5 V gate drive using NextPower Superjunction technology. It delivers 1.15 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C, supports 100 A continuous drain current at Tmb = 25 °C, and operates up to 175 °C junction temperature - enabling high-efficiency synchronous rectification and load switching in server power supplies.
For engineers reviewing the PSMN1R1-25YLC datasheet, PSMN1R1-25YLC pinout, PSMN1R1-25YLC application, or PSMN1R1-25YLC equivalent, key selection criteria include its ultra-low QG (39 nC @ 4.5 V), low parasitic inductance, 25 V VDS rating, and qualification to 175 °C for industrial-grade thermal reliability.
Technical Context
This MOSFET employs NextPower Superjunction architecture to minimize conduction and switching losses simultaneously. Its RDS(on) of 1.2 mΩ (typ.) at VGS = 4.5 V and 25 °C enables efficient operation with standard logic-level drivers, while ultra-low QGD (11 nC) and QOSS (22.6 nC) reduce switching energy and improve hard-switching performance.
The device features an integrated source-drain diode with 43 ns reverse recovery time and 42 nC recovered charge, supporting high-frequency synchronous rectification. Thermal resistance from junction to mounting base is 0.58 K/W (typ.), enabling high-power density designs when mounted on thermally optimized PCBs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 25 V - Maximum blocking voltage compatible with 24 V input rails and transient margin in DC-DC converters. |
| RDS(on) | 0.95–1.15 mΩ @ VGS = 10 V, Tj = 25 °C - Enables <1 W conduction loss at 100 A, critical for high-current power OR-ing. |
| QG(tot) | 39 nC @ VGS = 4.5 V - Low gate charge reduces driver power demand and improves efficiency in 500 kHz+ switching applications. |
| ID | 100 A continuous @ Tmb = 25 °C - Supports high-current load switching without external heatsinking in compact layouts. |
| Tj(max) | 175 °C - Qualified for extended thermal operation in industrial and communications equipment with limited airflow. |
| Rth(j-mb) | 0.58 K/W (typ.) - Enables >150 W power dissipation with ≤100 K rise above mounting base temperature. |
| VGS(th) | 1.05–1.95 V @ ID = 1 mA - Ensures reliable turn-on with 3.3 V or 5 V logic controllers without level-shifting. |
Pinout & Package
LFPAK (SOT669) is a 4-lead plastic single-ended surface-mounted package with exposed mounting base connected to drain. It provides low-inductance, high-current routing and superior thermal transfer versus SO-8.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three parallel source terminals reduce bond-wire inductance and improve current sharing in high-di/dt applications. |
| 4 | Gate (G) | Single gate input with 1.1 Ω typical gate resistance - simplifies gate driver design and damping requirements. |
| Mounting base (mb) | Drain (D) | Exposed copper drain pad soldered directly to PCB thermal plane - primary heat path and high-current return path. |
Key Features
| Feature | Design Value |
|---|---|
| NextPower Superjunction technology | Enables simultaneous ultra-low RDS(on) and QG, reducing both conduction and switching losses in high-frequency SMPS. |
| Optimized for 4.5 V gate drive | Guarantees full enhancement with standard microcontroller GPIO or low-voltage PWM controllers - no external level shifter needed. |
| Ultra-low QGD and QOSS | 11 nC QGD and 22.6 nC QOSS minimize Miller effect and output energy loss - critical for ZVS/ZCS topologies. |
| 175 °C qualified Power-SO8 package | Validated for long-term operation at elevated temperatures - eliminates derating concerns in sealed industrial enclosures. |
| Low parasitic inductance layout | Three-source-pin configuration and drain-connected mounting base reduce loop inductance by >30% vs. standard SO-8. |
Applications
| DC-DC Converters | Lithium-ion Battery Protection |
|---|---|
Use Scenario: High-current buck converter in telecom power shelf delivering 50 A at 12 V output. IC Role / Device Role / Timing Role: Synchronous rectifier replacing Schottky diode to reduce conduction loss and improve efficiency above 95%. Use Value: 1.15 mΩ RDS(on) cuts rectifier loss to <0.7 W at 50 A, enabling smaller heatsinks and higher power density. |
Use Scenario: Primary protection FET in multi-cell Li-ion pack management system with overcurrent cutoff. IC Role / Device Role / Timing Role: High-side load switch controlled by battery monitor IC to disconnect pack during fault conditions. Use Value: 100 A rated current and 175 °C Tj(max) ensure robust response to short-circuit events without thermal runaway. |
| Power OR-ing | Server Power Supplies |
Use Scenario: Redundant 48 V input OR-ing circuit in enterprise server PSU with dual AC inputs. IC Role / Device Role / Timing Role: Back-to-back N-channel MOSFET pair implementing low-loss, fast-turnoff OR-ing function. Use Value: Ultra-low QG (39 nC) enables sub-100 ns turn-off delay - preventing reverse current flow during input switchover. |
Use Scenario: 24 V intermediate bus converter supplying CPU VRMs in cloud data center servers. IC Role / Device Role / Timing Role: High-side switch in multiphase buck controller's power stage, operating at 600 kHz. Use Value: 0.58 K/W Rth(j-mb) allows direct thermal coupling to VRM heatsink - sustaining 85 °C case temp under full load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRL1404ZPBF | RDS(on) = 4.0 mΩ @ 4.5 V; QG = 42 nC; TO-220 package; 55 V rating | Higher RDS(on) increases conduction loss by ~3.5×; larger footprint and inferior thermal resistance (1.5 K/W). | Select only if 55 V rating is required and board space permits TO-220 mounting. |
| DMTH10H025LPS-13 | RDS(on) = 1.3 mΩ @ 4.5 V; QG = 48 nC; PowerDI5060 package; 25 V rating | Higher QG increases switching loss; no three-source-pin configuration - higher package inductance. | Preferable only if PowerDI5060 footprint compatibility is mandatory and gate drive strength exceeds 2 A peak. |
Compared with IRL1404ZPBF and DMTH10H025LPS-13, PSMN1R1-25YLC offers the lowest combined conduction-switching loss due to its 1.15 mΩ/39 nC balance and three-source-pin LFPAK layout - making it optimal for high-current, high-frequency server and telecom power stages where thermal and EMI constraints are tight.
Availability
PSMN1R1-25YLC is available at Aetrix Electronics and suitable for server power supplies, lithium-ion battery protection circuits, DC-DC converters, and power OR-ing applications requiring stable component supply across industrial and communications equipment lifecycles.
Supply support for PSMN1R1-25YLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified and industrial-grade MOSFETs.
This device belongs to Nexperia's NextPower Superjunction MOSFET product line, engineered specifically for high-efficiency, high-current switching in 24–48 V power systems such as data center PSUs and industrial DC distribution.
FAQ
What is the maximum continuous drain current for PSMN1R1-25YLC at 100 °C mounting base temperature?
At Tmb = 100 °C, the continuous drain current is derated to 100 A per Figure 1 in the datasheet - identical to its rating at 25 °C because the limiting factor is package thermal capacity, not silicon current density. This reflects the robustness of the LFPAK construction and its low Rth(j-mb).
Does PSMN1R1-25YLC require a gate resistor for stability in high-speed switching?
Yes - a 4.7 Ω external gate resistor is recommended (per Figure 14 test conditions) to damp ringing caused by interaction between its 1.1 Ω intrinsic gate resistance and PCB trace inductance. Omitting it risks overshoot exceeding ±20 V VGS limits during 100 A/ns edge rates.
Can PSMN1R1-25YLC be used in avalanche mode for unclamped inductive switching?
Yes - it is rated for 253 mJ non-repetitive drain-source avalanche energy (EDS(AL)S) at Tj(init) = 25 °C, ID = 100 A, and Vsup ≤25 V. This capability supports robustness in motor drive freewheeling and relay snubbing, provided single-pulse conditions are strictly observed.
How does the three-source-pin configuration impact PCB layout compared to standard SO-8 MOSFETs?
The three-source pins (pins 1–3) must be routed with equal-length, wide copper pours to ensure balanced current division and minimize asymmetrical heating. Unlike standard SO-8, this configuration reduces source loop inductance by 35% - critical for minimizing voltage spikes in >100 A switching nodes.
PSMN1R1-25YLC,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SC-100, SOT-669
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 25 V
- Current - Continuous Drain (Id) @ 25°C:
- 100A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 1.15mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 1.95V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 83 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 5287 pF @ 12 V
- FET Feature:
- -
- Power Dissipation (Max):
- 215W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56, Power-SO8
PSMN1R1-25YLC,115 FAQ
1.How can I place an order for PSMN1R1-25YLC,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN1R1-25YLC,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN1R1-25YLC,115 reliable?
The price and inventory of PSMN1R1-25YLC,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R1-25YLC,115 is usually 5 days.
3.What payment methods are accepted for PSMN1R1-25YLC,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN1R1-25YLC,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN1R1-25YLC,115?
PSMN1R1-25YLC,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN1R1-25YLC,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN1R1-25YLC,115?
For technical support, including PSMN1R1-25YLC,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R1-25YLC,115 requirements.
6.How does Aetrix verify that PSMN1R1-25YLC,115 is sourced from the original manufacturer or authorized distributors?
All PSMN1R1-25YLC,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R1-25YLC,115 meets industry standards.
7.What is the process for return or replacement of PSMN1R1-25YLC,115?
All PSMN1R1-25YLC,115 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R1-25YLC,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN1R1-25YLC,115 part is unused and in its original packaging.
Return procedure for PSMN1R1-25YLC,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PSMN1R1-25YLC,115 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
