Nexperia USA Inc. PSMN1R2-25YL,115
- Part No.:
- PSMN1R2-25YL,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SOT-1023, 4-LFPAK
- Datasheet:
-
PSMN1R2-25YL,115.pdf
- Description:
- MOSFET N-CH 25V 100A LFPAK56
- Quantity:
- Payment:

- Shipping:

Inventory:29,817
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PSMN1R2-25YL from Nexperia is a logic-level N-channel MOSFET in LFPAK2 (SOT1023) package, rated for 25 V VDS, 1.2 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C, 100 A continuous drain current at Tmb = 25 °C, and qualified to 150 °C junction temperature - deployed in high-current load switching and server power supply rails.
For engineers reviewing the PSMN1R2-25YL datasheet, PSMN1R2-25YL pinout, PSMN1R2-25YL application, or PSMN1R2-25YL equivalent, key selection criteria include low RDS(on) at 4.5 V gate drive, avalanche energy rating (677 mJ), thermal resistance (Rth(j-mb) = 0.4 K/W), and LFPAK2 mechanical robustness for high-power density PCB layouts.
Technical Context
This MOSFET uses Nexperia's Advanced TrenchMOS technology to achieve ultra-low on-resistance and gate charge - enabling high-efficiency operation in synchronous rectification and high-frequency DC-DC converters. Its logic-level gate threshold (VGS(th) = 1.3–2.15 V typ.) ensures full enhancement with standard 3.3 V or 5 V microcontroller outputs.
The device features an integrated source-drain diode with 52 ns reverse recovery time and 66 nC recovered charge, supporting fast commutation in motor control and battery protection circuits. Thermal design is enabled by direct die-to-mounting-base conduction path (Rth(j-mb) = 0.4 K/W typ.), making it suitable for thermally constrained industrial power modules.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 25 V - Maximum blocking voltage for 24 V system rail protection and Li-ion battery stack switching |
| RDS(on) | 0.9–1.2 mΩ @ VGS = 10 V, Tj = 25 °C - Enables <1 W conduction loss at 100 A, critical for server PSU efficiency |
| ID | 100 A continuous @ Tmb = 25 °C - Limited by LFPAK2 package thermal capability, not silicon |
| EAS | 677 mJ non-repetitive avalanche energy - Supports unclamped inductive switching in motor drives without external snubbers |
| QG(tot) | 50.6 nC @ VGS = 4.5 V - Low gate drive power requirement for 3.3 V logic control in compact power stages |
| Rth(j-mb) | 0.4 K/W typ. - Enables >100 W dissipation with modest heatsinking, reducing need for large copper areas |
| VGS(th) | 1.3–2.15 V @ Tj = 25 °C - Ensures reliable turn-on with standard logic-level drivers across temperature |
Pinout & Package
PSMN1R2-25YL is housed in the LFPAK2 (SOT1023) surface-mount package - a reinforced Power SO8 variant with exposed drain pad for enhanced thermal and mechanical performance. The package features three parallel source terminals and one gate terminal, optimized for high-current PCB routing and low-inductance layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 (S) | Source | Three paralleled source terminals reduce bond-wire inductance and increase current-carrying capacity; connected internally to source metallization |
| 4 (G) | Gate | Single gate input with 0.94 Ω intrinsic gate resistance - minimizes ringing in high-dI/dt switching |
| Drain (mb) | Drain (exposed pad) | Thermally and electrically connected mounting base - serves as primary drain connection and heat path to PCB copper |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level gate drive | Operates fully enhanced at VGS = 4.5 V, compatible with 3.3 V/5 V MCU GPIOs without level-shifting |
| Ultra-low RDS(on) | 1.2 mΩ max @ 10 V/25 °C enables <1.2 W conduction loss at 100 A - reduces thermal derating in dense power modules |
| LFPAK2 package | SOT1023 footprint delivers 3× higher power density than standard SO8, with 0.4 K/W thermal resistance to mounting base |
| Avalanche ruggedness | 677 mJ EAS supports safe operation under inductive load interruption - eliminates need for external clamping in many motor/battery applications |
Applications
| DC-DC Converters | Lithium-ion Battery Protection |
|---|---|
|
Use Scenario: High-current synchronous buck converter in telecom power supplies operating at 300–500 kHz. IC Role / Device Role / Timing Role: Low-side switch handling up to 100 A continuous current with minimal conduction loss. Use Value: 1.2 mΩ RDS(on) reduces conduction loss by >40% vs. comparable 2.5 mΩ MOSFETs, improving full-load efficiency by ~1.2%. |
Use Scenario: Primary overcurrent and short-circuit protection in 4S–12S Li-ion battery packs for power tools. IC Role / Device Role / Timing Role: Main discharge FET controlled by battery management IC, requiring fast turn-off and avalanche tolerance. Use Value: 677 mJ avalanche energy withstands fault currents without failure; 52 ns trr enables rapid current cutoff during cell imbalance events. |
| Server Power Supplies | Motor Control |
|
Use Scenario: 12 V input VRM stage delivering >80 A to CPU/GPU cores in datacenter servers. IC Role / Device Role / Timing Role: High-current power stage switch with tight thermal constraints on multilayer PCBs. Use Value: 0.4 K/W Rth(j-mb) allows >100 W dissipation with 2 oz copper and thermal vias - avoids costly heatsinks. |
Use Scenario: H-bridge low-side driver in 24 V BLDC motor controllers for industrial automation. IC Role / Device Role / Timing Role: Fast-switching, high-current switch managing PWM commutation at 20–40 kHz. Use Value: 50.6 nC QG at 4.5 V enables efficient gate driving from low-voltage MCUs; 125 ns tr supports clean edge transitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRL1404ZPBF | RDS(on) = 3.2 mΩ @ 10 V/25 °C; TO-220 package; Rth(j-c) = 1.25 K/W | Higher conduction loss and inferior thermal performance - requires larger heatsink in high-current apps | Choose only when through-hole assembly or legacy footprint compatibility is mandatory |
| DMTH10H025LPSQ | RDS(on) = 1.0 mΩ @ 10 V/25 °C; LFPAK56 package; 150 °C rated; QG = 42 nC @ 4.5 V | Lower gate charge and marginally better RDS(on), but higher cost and longer lead times | Prefer for new designs demanding highest efficiency and fastest switching, if cost and availability permit |
Compared with IRL1404ZPBF, PSMN1R2-25YL delivers 2.7× lower RDS(on) and 3× better thermal resistance; versus DMTH10H025LPSQ, it trades 0.2 mΩ RDS(on) and 8.6 nC QG for broader supply chain availability and lower unit cost in high-volume production.
Availability
PSMN1R2-25YL is available at Aetrix Electronics and suitable for server power supplies, lithium-ion battery protection circuits, and high-current DC-DC converters requiring stable component supply and long-term industrial lifecycle support.
Supply support for PSMN1R2-25YL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential semiconductors - delivering high-performance, reliable components for automotive, industrial, and consumer applications.
This MOSFET belongs to Nexperia's Logic Level TrenchMOS portfolio, engineered specifically for high-efficiency, high-current switching in space-constrained power systems where thermal performance and gate-drive simplicity are critical.
FAQ
What is the maximum continuous drain current for PSMN1R2-25YL at 100 °C mounting base temperature?
The datasheet specifies 100 A continuous drain current at Tmb = 25 °C, derated to approximately 65 A at Tmb = 100 °C per Figure 1. This limitation is package-defined, not silicon-limited, and assumes adequate PCB copper area for thermal spreading.
Can PSMN1R2-25YL be driven directly from a 3.3 V microcontroller GPIO?
Yes - its gate threshold voltage ranges from 1.3 V to 2.15 V at 25 °C, and it achieves RDS(on) ≤ 1.85 mΩ at VGS = 4.5 V and Tj = 25 °C. At 3.3 V, typical RDS(on) is ~2.5 mΩ, sufficient for moderate-current applications; for full 100 A capability, 4.5 V or higher is recommended.
Does PSMN1R2-25YL have an integrated body diode, and what are its key parameters?
Yes - it includes a source-drain diode with forward voltage VSD = 0.78–1.2 V at IS = 25 A and Tj = 25 °C, reverse recovery time trr = 52 ns, and recovered charge Qr = 66 nC. These values support efficient freewheeling in synchronous rectifiers and H-bridge motor drives.
What is the recommended PCB layout practice for optimal thermal performance of PSMN1R2-25YL?
Maximize copper area connected to the exposed drain pad (mb) using ≥8 thermal vias (0.3 mm diameter) to inner ground/power planes. Use ≥2 oz copper on top and inner layers, and ensure uninterrupted thermal paths to chassis or heatsink. Source pins (1–3) should be routed with wide, low-inductance traces to minimize switching loop area.
PSMN1R2-25YL,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SOT-1023, 4-LFPAK
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 25 V
- Current - Continuous Drain (Id) @ 25°C:
- 100A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 1.2mOhm @ 15A, 10V
- Vgs(th) (Max) @ Id:
- 2.15V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 105 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 6380 pF @ 12 V
- FET Feature:
- -
- Power Dissipation (Max):
- 121W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56; Power-SO8
PSMN1R2-25YL,115 FAQ
1.How can I place an order for PSMN1R2-25YL,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN1R2-25YL,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN1R2-25YL,115 reliable?
The price and inventory of PSMN1R2-25YL,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R2-25YL,115 is usually 5 days.
3.What payment methods are accepted for PSMN1R2-25YL,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN1R2-25YL,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN1R2-25YL,115?
PSMN1R2-25YL,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN1R2-25YL,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN1R2-25YL,115?
For technical support, including PSMN1R2-25YL,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R2-25YL,115 requirements.
6.How does Aetrix verify that PSMN1R2-25YL,115 is sourced from the original manufacturer or authorized distributors?
All PSMN1R2-25YL,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R2-25YL,115 meets industry standards.
7.What is the process for return or replacement of PSMN1R2-25YL,115?
All PSMN1R2-25YL,115 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R2-25YL,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN1R2-25YL,115 part is unused and in its original packaging.
Return procedure for PSMN1R2-25YL,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PSMN1R2-25YL,115 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

