Nexperia USA Inc. PSMN1R2-25YLC,115

Overview

PSMN1R2-25YLC from Nexperia is a logic-level enhancement-mode N-channel MOSFET in LFPAK (SOT669) package, optimized for 4.5 V gate drive using NextPower Superjunction technology. It delivers 1.35 mΩ R_DS(on) at V_GS = 4.5 V / I_D = 25 A / T_j = 25 °C, supports 100 A continuous drain current at T_mb = 25 °C, and operates up to 175 °C junction temperature - deployed in server power supplies and synchronous rectification circuits.

For engineers reviewing the PSMN1R2-25YLC datasheet, PSMN1R2-25YLC pinout, PSMN1R2-25YLC application, or PSMN1R2-25YLC equivalent, key selection criteria include low-voltage gate drive compatibility, ultra-low Q_G/Q_GD, thermal resistance (R_th(j-mb) = 0.71 K/W), avalanche ruggedness (178 mJ), and LFPAK package mounting base thermal interface performance.

Technical Context

This MOSFET employs NextPower Superjunction architecture to minimize conduction and switching losses simultaneously. Its gate threshold voltage (V_GS(th) = 1.05–1.95 V at T_j = 25 °C) ensures reliable turn-on with standard logic-level drivers, while ultra-low Q_GD (8.3 nC) and Q_G(tot) (31 nC at 4.5 V) reduce switching energy and improve efficiency across load ranges.

The device integrates a robust body diode with t_rr = 41 ns and Q_r = 36 nC, enabling high-frequency synchronous rectification. Thermal design is anchored to the mounting base (D-pin), with R_th(j-mb) = 0.71 K/W enabling high-power density layouts without external heatsinks in many applications.

Key Specifications

Pinout & Package

PSMN1R2-25YLC uses the SOT669 (LFPAK; Power-SO8) plastic surface-mount package with exposed mounting base (D) for thermal and electrical connection to drain. The package features three parallel source terminals and one gate terminal, optimized for low-inductance, high-current PCB routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.

Compared with PSMN2R0-25YLH,115, this part trades 0.65 mΩ lower R_DS(on) for +6 nC Q_G, favoring medium-frequency, high-current use cases; versus IRLHS6342TRPBF, it delivers 7× better thermal resistance and 3× higher current rating in identical footprint-class packaging.

Availability

PSMN1R2-25YLC is available at Aetrix Electronics and suitable for server power supplies, lithium-ion battery protection circuits, synchronous rectification stages, and power OR-ing applications requiring stable component supply, long-term industrial lifecycle support, and traceable sourcing.

Supply support for PSMN1R2-25YLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors - high-volume, high-reliability discrete, logic, and MOSFET devices engineered for industrial, computing, and communications infrastructure.

This device belongs to Nexperia's NextPower Superjunction MOSFET product line, designed specifically for high-efficiency, high-current switching in 12–48 V power conversion systems where low R_DS(on), fast switching, and thermal robustness are critical.

FAQ

What is the maximum continuous drain current for PSMN1R2-25YLC at 100 °C mounting base temperature?

At T_mb = 100 °C, the continuous drain current is derated to 100 A - identical to its rating at 25 °C - because the LFPAK package's thermal resistance to mounting base (0.71 K/W) and high-temperature silicon design maintain current capability up to that point. Derating begins above 100 °C per Figure 1 in the datasheet.

Can PSMN1R2-25YLC be used in avalanche mode, and what is its rated energy?

Yes - PSMN1R2-25YLC is rated for non-repetitive drain-source avalanche energy of 178 mJ at T_j(init) = 25 °C, I_D = 100 A, V_sup ≤25 V, unclamped, with R_GS = 50 Ω. This rating supports single-event transient suppression in OR-ing and load-switching applications but is not intended for repetitive avalanche operation.

How does the LFPAK package improve thermal performance compared to standard SO-8?

The LFPAK (SOT669) package exposes the drain as a large copper mounting base directly soldered to PCB copper, achieving R_th(j-mb) = 0.71 K/W - over 30× lower than typical SO-8 R_th(j-a). This enables >100 A continuous current handling without external heatsinks, whereas SO-8 variants are typically limited to <20 A in similar layouts.

Is PSMN1R2-25YLC suitable for driving with a 3.3 V microcontroller GPIO pin?

Yes - with V_GS(th) = 1.05–1.95 V and guaranteed R_DS(on) ≤1.7 mΩ at V_GS = 4.5 V, the device fully enhances using 3.3 V logic when paired with a low-impedance driver (e.g., dedicated gate driver or buffered MCU output). However, for 100 A switching, a dedicated driver is recommended to ensure fast dV/dt control and minimize switching loss.