Nexperia USA Inc. PSMN1R2-80ASEJ
- Part No.:
- PSMN1R2-80ASEJ
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- 12-BESOP (0.370", 9.40mm Width), Exposed Pad
- Datasheet:
-
PSMN1R2-80ASEJ.pdf
- Description:
- N-CHANNEL, 80 V, 1.18 MOHM, MOSF
- Quantity:
- Payment:

- Shipping:

Inventory:9,426
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Product details
Overview
PSMN1R2-80ASEJ from Nexperia is an N-channel enhancement-mode MOSFET in CCPAK1212 (SOT8000A) package, rated for 80 V VDS, 1.18 mΩ RDS(on) at 10 V VGS, and qualified to 175 °C junction temperature. It delivers high-current capability (375 A continuous at Tmb = 25 °C), enhanced Safe Operating Area (SOA) for linear-mode hot-swap control, and low thermal resistance (0.123 K/W Rth(j-mb)). Used in 48 V telecom backplane e-fuse and soft-start circuits.
For engineers reviewing the PSMN1R2-80ASEJ datasheet, PSMN1R2-80ASEJ pinout, PSMN1R2-80ASEJ application, or PSMN1R2-80ASEJ equivalent, this page provides verified SOA performance data, CCPAK1212 terminal mapping, hot-swap current-limiting design context, and validated alternatives for high-reliability load switching.
Technical Context
This MOSFET employs a copper-clip CCPAK1212 package with 12 drain terminals plus mounting base (drain-connected), enabling ultra-low Rth(j-mb) and robust pulsed avalanche energy handling (1300 mJ). Its gate threshold voltage (2.8 V typ at 25 °C) and plateau voltage (4.7 V) support stable turn-on with commercial hot-swap controllers.
The device features fully optimized SOA up to 100 ms pulse width at 80 V, with linear-mode operation validated across -55 °C to 175 °C. Dynamic parameters-including 233 nC total gate charge and 27.3 nC QGD-are specified under standardized 40 V VDS, 25 A ID conditions at 25 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 80 V - Maximum drain-source blocking voltage; supports 48 V rail systems with 66 % derating margin. |
| RDS(on) | 1.18 mΩ @ VGS = 10 V, ID = 25 A, Tj = 25 °C - Enables <1 W conduction loss at 300 A, critical for high-efficiency hot-swap. |
| ID (cont) | 375 A @ Tmb = 25 °C - Validated continuous current; limited in practice by PCB thermal design and mounting base temperature. |
| EAS | 1300 mJ - Non-repetitive avalanche energy at Tj(init) = 25 °C; withstands unclamped inductive turn-off transients in e-fuse applications. |
| Rth(j-mb) | 0.123 K/W - Junction-to-mounting-base thermal resistance; enables >900 W power dissipation with 115 K ΔT to heatsink. |
| QG(tot) | 233 nC @ VDS = 40 V, ID = 25 A - Gate drive energy requirement determines controller selection and switching loss trade-offs. |
| tr/tf | 57 ns / 70 ns - Fast switching transitions reduce overlap loss during hard-switched soft-start sequencing. |
Pinout & Package
CCPAK1212 (SOT8000A) is a surface-mount copper-clip package measuring 12 mm × 12 mm × 2.5 mm with 13 terminals: 1 gate, 4 source, 6 drain, and 1 exposed mounting base electrically tied to drain. JEDEC-qualified for open-market compatibility and second-source procurement.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | G | Gate input - Low-impedance control node; requires <5 Ω external gate resistor to damp oscillation during fast switching. |
| 2–5 | S | Source return - Four parallel source terminals minimize common-source inductance in high-di/dt load-switch paths. |
| 7–12 | D | Drain power path - Six drain terminals distribute current and reduce package inductance below 1.5 nH for EMI-sensitive telecom use. |
| mb | D (mounting base) | Drain-connected thermal interface - Directly soldered to heatsink or PCB copper pour; primary heat extraction path (Rth(j-mb) = 0.123 K/W). |
Key Features
| Feature | Design Value |
|---|---|
| Fully optimized SOA | Validated linear-mode operation up to 100 ms at 80 V - enables controlled current ramp during hot-swap insertion without thermal runaway. |
| Ultra-low RDS(on) | 1.18 mΩ max at 25 °C - reduces I²R losses to <1.1 W at 330 A, improving system efficiency and easing thermal management. |
| CCPAK1212 package | JEDEC-listed SOT8000A with 12 mm × 12 mm footprint - delivers 3× lower Rth(j-mb) vs. TO-263 and supports >375 A continuous current on standard FR4. |
| High-temperature rating | 175 °C Tj max - enables operation in sealed telecom enclosures with ambient temperatures up to 105 °C. |
| Avalanche ruggedness | 1300 mJ EAS (100 % tested) - protects against inductive kickback during fault clearing in e-fuse implementations. |
Applications
| Hot Swap Controller Interface | 48 V Telecom Backplane Load Switch |
|---|---|
|
Use Scenario: Insertion of line cards into live 48 V backplane without causing bus voltage droop or controller latch-up. IC Role / Device Role / Timing Role: Main power FET in discrete or integrated hot-swap circuit; operates in linear mode during current ramp, then saturated during steady-state. Use Value: Enhanced SOA prevents thermal failure during 50–200 ms inrush; 1.18 mΩ RDS(on) limits voltage drop to <0.4 V at 300 A, preserving downstream rail stability. |
Use Scenario: Controlled power-up of redundant power modules in carrier-grade routers with strict inrush limits. IC Role / Device Role / Timing Role: High-side load switch managed by dedicated hot-swap IC (e.g., LTC4215); handles full 48 V/300 A load after soft-start completion. Use Value: 375 A continuous rating allows single-device implementation instead of paralleled TO-220 devices; CCPAK1212 mounting base ensures reliable thermal coupling to chassis. |
| E-Fuse Protection Circuit | Soft-Start Sequencing for Server PSUs |
|
Use Scenario: Replacing electromechanical fuses in 48 V intermediate bus distribution with electronic overcurrent protection. IC Role / Device Role / Timing Role: Current-sensing power switch; conducts normally, shuts off within microseconds upon overcurrent detection via external sense amplifier. Use Value: 1300 mJ avalanche energy rating absorbs energy from short-circuit events before protection triggers; low RDS(on) minimizes sense resistor power loss. |
Use Scenario: Gradual ramp-up of 48 V input to server power supply inputs to limit inrush into bulk capacitors. IC Role / Device Role / Timing Role: Linear-mode pass element controlled by op-amp-based soft-start circuit; regulates dV/dt across output capacitor bank. Use Value: SOA curve validated to 100 ms at 80 V enables precise 100–500 ms ramp times without thermal stress; 175 °C rating supports compact enclosure designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-current, high-SOA N-channel MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon IPP026N08N | RDS(on) = 2.6 mΩ (higher), SOA not characterized beyond 10 ms, TO-220FP package (Rth(j-a) = 45 K/W). | Limited to lower-current hot-swap (<150 A); unsuitable for sustained linear-mode operation above 50 ms. | Select only if cost sensitivity outweighs SOA and thermal performance requirements. |
| Vishay SiR626DP | RDS(on) = 1.25 mΩ, PowerPAK® 1212-8 package (Rth(j-mb) = 0.21 K/W), no published SOA curves beyond 10 ms. | Acceptable for soft-start but lacks validated 100 ms SOA; lower thermal performance increases heatsink size by ~40 %. | Prefer when existing layout uses PowerPAK 1212-8 footprint and SOA duration <20 ms suffices. |
Compared with IPP026N08N and SiR626DP, PSMN1R2-80ASEJ offers superior SOA endurance (100 ms vs. ≤10 ms), lower thermal resistance (0.123 vs. ≥0.21 K/W), and JEDEC-standardized CCPAK1212 packaging-making it uniquely suited for telecom-grade hot-swap and e-fuse where reliability under sustained linear stress is non-negotiable.
Availability
PSMN1R2-80ASEJ is available at Aetrix Electronics and suitable for 48 V telecom backplane load switching, hot-swap controller interfacing, and e-fuse protection requiring stable component supply across extended product lifecycles.
Supply support for PSMN1R2-80ASEJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and discrete components, with manufacturing sites in Europe, Asia, and the Americas.
PSMN1R2-80ASEJ belongs to Nexperia's Application Specific MOSFETs (ASFETs) portfolio, engineered specifically for hot-swap, soft-start, and e-fuse functions in high-voltage DC infrastructure where SOA integrity and thermal robustness are critical.
FAQ
What is the maximum continuous drain current for PSMN1R2-80ASEJ at 100 °C mounting base temperature?
At Tmb = 100 °C, the continuous drain current is 375 A per Figure 2 of the datasheet-same as at 25 °C-because thermal derating begins only above 100 °C. This reflects the exceptional thermal performance of the CCPAK1212 package, though practical current remains constrained by PCB copper area and heatsink interface quality.
Does PSMN1R2-80ASEJ require gate resistors for stable hot-swap operation?
Yes. A 4.7 Ω to 10 Ω series gate resistor is recommended to control dV/dt and prevent oscillation during linear-mode transitions. The device's 233 nC QG(tot) and low gate resistance (1.05 Ω typ) make it susceptible to ringing without proper gate drive damping, especially when paired with high-speed hot-swap controllers.
Can PSMN1R2-80ASEJ be used in automotive applications?
No. PSMN1R2-80ASEJ is not AEC-Q101 qualified and lacks automotive-specific testing (e.g., HTOL, UHAST, ESD HBM ≥2 kV). Its 175 °C rating applies to industrial/telecom use only; Nexperia explicitly states non-automotive qualification in Section 13 of the datasheet.
How is the mounting base (mb) terminal electrically connected internally?
The mounting base is directly bonded to the drain die metallization and is electrically identical to pins 7–12. It must be soldered to a large copper pour or heatsink and treated as part of the drain current path-not as a separate thermal pad. No isolation or insulation is required between mb and drain traces.
PSMN1R2-80ASEJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 12-BESOP (0.370", 9.40mm Width), Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 80 V
- Current - Continuous Drain (Id) @ 25°C:
- 375A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 1.18mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 3.6V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 350 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 26187 pF @ 40 V
- FET Feature:
- -
- Power Dissipation (Max):
- 935W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- CCPAK1212
PSMN1R2-80ASEJ FAQ
1.How can I place an order for PSMN1R2-80ASEJ through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN1R2-80ASEJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN1R2-80ASEJ reliable?
The price and inventory of PSMN1R2-80ASEJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R2-80ASEJ is usually 5 days.
3.What payment methods are accepted for PSMN1R2-80ASEJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN1R2-80ASEJ transactions.
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4.How is shipping managed for PSMN1R2-80ASEJ?
PSMN1R2-80ASEJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN1R2-80ASEJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN1R2-80ASEJ?
For technical support, including PSMN1R2-80ASEJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R2-80ASEJ requirements.
6.How does Aetrix verify that PSMN1R2-80ASEJ is sourced from the original manufacturer or authorized distributors?
All PSMN1R2-80ASEJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R2-80ASEJ meets industry standards.
7.What is the process for return or replacement of PSMN1R2-80ASEJ?
All PSMN1R2-80ASEJ units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R2-80ASEJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN1R2-80ASEJ part is unused and in its original packaging.
Return procedure for PSMN1R2-80ASEJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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