Nexperia USA Inc. PSMN1R4-100CSEJ
- Part No.:
- PSMN1R4-100CSEJ
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- 12-BESOP (0.370", 9.40mm Width), Exposed Pad
- Datasheet:
-
PSMN1R4-100CSEJ.pdf
- Description:
- N-CHANNEL, 100 V, 1.42 MOHM, MOS
- Quantity:
- Payment:

- Shipping:

Inventory:9,602
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Product details
Overview
PSMN1R4-100CSE from Nexperia is an N-channel enhancement-mode MOSFET in a CCPAK1212i (SOT8005A) copper-clip package, rated for 100 V VDS, 1.42 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C, and qualified to 175 °C junction temperature. It delivers 340 A continuous drain current at Tmb = 25 °C and is engineered for hot-swap, soft-start, and e-fuse applications in 48 V telecom backplane systems.
For engineers reviewing the PSMN1R4-100CSE datasheet, PSMN1R4-100CSE pinout, PSMN1R4-100CSE application, or PSMN1R4-100CSE equivalent, key selection criteria include its enhanced SOA for linear-mode robustness, ultra-low RDS(on), top-side cooling capability, JEDEC-qualified CCPAK1212i package, and avalanche energy rating of 1130 mJ.
Technical Context
This MOSFET employs an inverted-package architecture with the mounting base electrically connected to the drain, enabling direct top-side thermal interface to heatsinks. Its SOA is fully optimized for sustained linear-mode operation-critical for controlled inrush current limiting during hot-swap turn-on.
The device features low gate charge (QG(tot) = 244 nC typ), fast switching (tr = 66 ns, tf = 86 ns), and high avalanche ruggedness (IAS = 98.95 A, EAS = 1130 mJ), supporting reliable operation under transient overloads without external snubbers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 100 V - Withstands full 48 V rail transients up to 100 V without breakdown. |
| RDS(on) | 1.42 mΩ @ VGS = 10 V, Tj = 25 °C - Enables <1 W conduction loss at 300 A, minimizing thermal stress. |
| ID (cont) | 340 A @ Tmb = 25 °C - Supports high-current load switching without derating due to copper-clip thermal path. |
| Ptot | 935 W @ Tmb = 25 °C - Highest power dissipation among 100 V discrete MOSFETs in surface-mount packages. |
| Rth(j-mb) | 0.123 K/W - Junction-to-mounting-base thermal resistance enables efficient top-side cooling. |
| EAS | 1130 mJ - Unclamped avalanche energy rating verified by 100% production test for surge resilience. |
| QG(tot) | 244 nC - Optimized gate charge supports fast, low-loss switching with standard gate drivers. |
Pinout & Package
CCPAK1212i (SOT8005A) is a 12-terminal, 12 mm × 12 mm × 2.5 mm surface-mount copper-clip package with exposed drain thermal pad on the top side. The inverted layout places source terminals on the bottom die attach side and drain/mounting base on top, enabling direct heatsink attachment.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–5 | Source | Five parallel low-inductance source connections reduce common-source inductance and improve switching stability. |
| 6 | Gate | Single gate input with 1.03 Ω typical gate resistance-optimized for drive strength and ringing suppression. |
| 7–12 | Drain | Six parallel drain terminals tied to the mounting base-distributes high current and enhances thermal conduction. |
| mb | Mounting Base (Drain) | Electrically connected to drain; serves as primary thermal interface for top-side cooling and mechanical anchoring. |
Key Features
| Feature | Design Value |
|---|---|
| Fully optimized SOA | Linear-mode safe operating area validated across Tj = 25–175 °C-enables stable current limiting without thermal runaway. |
| Inverted CCPAK1212i | Top-side drain/mounting base allows direct heatsink mounting-eliminates need for thermal vias or secondary cooling layers. |
| JEDEC-qualified package | SOT8005A footprint ensures second-source compatibility and standardized PCB layout across suppliers. |
| 175 °C qualification | Extended junction temperature rating supports operation in sealed telecom enclosures without forced airflow. |
| 100% avalanche tested | Every unit undergoes unclamped inductive switching test-guarantees minimum 1130 mJ EAS performance. |
Applications
| Hot Swap | Load Switch |
|---|---|
Use Scenario: Insertion of line cards into live 48 V telecom backplanes without disrupting system voltage or triggering upstream protection. IC Role / Device Role / Timing Role: Main power FET in hot-swap controller circuit-operates in linear mode during ramp-up, then fully ON during steady state. Use Value: Enhanced SOA prevents thermal failure during 10–100 ms inrush events; 1.42 mΩ RDS(on) limits steady-state power loss to <1.3 W at 200 A. | Use Scenario: High-current DC distribution switching in server PSUs and industrial power supplies. IC Role / Device Role / Timing Role: Primary load switch controlling 300+ A output rails-requires low conduction loss and high peak current capability. Use Value: 340 A continuous rating and 2140 A pulsed current support enable single-FET solutions for 1 kW+ loads; top-side cooling simplifies thermal design. |
| Soft Start | E-fuse |
Use Scenario: Controlled ramp-up of capacitive loads (e.g., bulk capacitance in base station RF modules) to limit inrush. IC Role / Device Role / Timing Role: Linear-mode current limiter-gate driven by error amplifier to regulate dV/dt and peak current. Use Value: SOA curve supports >100 ms linear operation at 100 A/50 V-avoids need for external current-sense amplifiers or complex feedback loops. | Use Scenario: Overcurrent protection for 48 V battery backup systems and distributed power architectures. IC Role / Device Role / Timing Role: Solid-state fuse element-monitored by controller to detect fault and shut down within microseconds. Use Value: 1130 mJ avalanche energy withstands short-circuit energy before shutdown; 1.42 mΩ RDS(on) minimizes voltage drop during normal operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-current, high-SOA MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IXTN300N10L2 | Trench-based TO-264 package; RDS(on) = 1.0 mΩ but lower SOA margin and no top-side cooling. | Requires bottom-side cooling only; less suitable for space-constrained telecom modules with limited PCB thermal mass. | Prefer when lowest possible RDS(on) is critical and board-level thermal design permits through-hole mounting. |
| STW100N10F7 | TO-247-4L package; RDS(on) = 1.25 mΩ; QG = 190 nC; no 100% avalanche test. | Lacks JEDEC-qualified surface-mount footprint and top-side thermal interface-limits use in high-density telecom boards. | Choose when cost sensitivity outweighs top-side cooling requirement and JEDEC footprint compliance is not mandatory. |
Compared with IXTN300N10L2 and STW100N10F7, PSMN1R4-100CSE uniquely combines JEDEC-standardized SMT packaging, top-side thermal interface, 100% avalanche testing, and SOA-optimized linear-mode operation-making it the only solution qualified for next-generation compact, high-reliability hot-swap modules.
Availability
PSMN1R4-100CSE is available at Aetrix Electronics and suitable for hot-swap controllers, telecom load switches, soft-start circuits, and e-fuse implementations requiring stable component supply, long-term lifecycle assurance, and JEDEC-compliant sourcing.
Supply support for PSMN1R4-100CSE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies-delivering high-performance, high-reliability discrete and logic devices for automotive, industrial, and computing markets.
PSMN1R4-100CSE belongs to Nexperia's Application Specific MOSFETs (ASFETs) product line, designed specifically for high-current, high-SOA linear-mode applications including hot-swap, soft-start, and electronic fuse functions in 48 V infrastructure systems.
FAQ
What is the maximum continuous drain current for PSMN1R4-100CSE at 100 °C mounting base temperature?
At Tmb = 100 °C, the continuous drain current remains 340 A per Figure 2 of the datasheet-verified in application tests. Practical current is limited by PCB copper area, thermal interface quality, and ambient conditions-not by device derating.
Can PSMN1R4-100CSE be used with bottom-side cooling only?
No-the CCPAK1212i package is inverted: the mounting base (drain) is on top and thermally isolated from the PCB. Bottom-side cooling is ineffective; thermal design must use top-side heatsink contact with the exposed drain pad.
Is the gate threshold voltage (VGS(th)) stable across temperature?
Yes-VGS(th) exhibits a negative temperature coefficient of −6.93 mV/K (25–150 °C), dropping from 2.8 V typ at 25 °C to 1.76 V typ at 175 °C. This improves turn-on robustness at high temperature but requires gate drive headroom verification.
Does PSMN1R4-100CSE require special PCB layout considerations for thermal performance?
Yes-optimal thermal performance requires a 25.4 mm square copper area (70 µm thick) on FR4 per Figure 7, plus solder paste stencil thickness of 0.1 mm (Figure 19). The mounting base must be soldered directly to a heatsink or thermal pad with minimal interfacial resistance.
PSMN1R4-100CSEJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 12-BESOP (0.370", 9.40mm Width), Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 100 V
- Current - Continuous Drain (Id) @ 25°C:
- 340A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 1.42mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 3.6V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 366 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 26023 pF @ 50 V
- FET Feature:
- -
- Power Dissipation (Max):
- 935W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- CCPAK1212i
PSMN1R4-100CSEJ FAQ
1.How can I place an order for PSMN1R4-100CSEJ through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN1R4-100CSEJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN1R4-100CSEJ reliable?
The price and inventory of PSMN1R4-100CSEJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R4-100CSEJ is usually 5 days.
3.What payment methods are accepted for PSMN1R4-100CSEJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN1R4-100CSEJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN1R4-100CSEJ?
PSMN1R4-100CSEJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN1R4-100CSEJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN1R4-100CSEJ?
For technical support, including PSMN1R4-100CSEJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R4-100CSEJ requirements.
6.How does Aetrix verify that PSMN1R4-100CSEJ is sourced from the original manufacturer or authorized distributors?
All PSMN1R4-100CSEJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R4-100CSEJ meets industry standards.
7.What is the process for return or replacement of PSMN1R4-100CSEJ?
All PSMN1R4-100CSEJ units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R4-100CSEJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN1R4-100CSEJ part is unused and in its original packaging.
Return procedure for PSMN1R4-100CSEJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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