Nexperia USA Inc. PSMN1R4-30YLD/2X
- Part No.:
- PSMN1R4-30YLD/2X
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SC-100, SOT-669
- Datasheet:
-
PSMN1R4-30YLD/2X.pdf
- Description:
- PSMN1R4-30YLD/SOT669/LFPAK
- Quantity:
- Payment:

- Shipping:

Inventory:7,402
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PSMN1R4-30YLD from Nexperia is an N-channel 30 V logic-level power MOSFET in LFPAK56 (SOT669) package, featuring 1.4 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C, ultra-low QG (27.6 nC at 4.5 V), and SchottkyPlus body diode with soft-recovery (s-factor > 0.99). It serves as a high-efficiency synchronous rectifier or main switch in DC-DC converters for server and telecom infrastructure.
For engineers reviewing the PSMN1R4-30YLD datasheet, PSMN1R4-30YLD pinout, PSMN1R4-30YLD application, or PSMN1R4-30YLD equivalent, key selection criteria include gate-drive compatibility at 4.5 V, thermal resistance to mounting base (0.81 K/W), avalanche ruggedness (653 mJ), and LFPAK56 package suitability for high-current, low-inductance PCB layouts.
Technical Context
This MOSFET employs Nexperia's NextPowerS3 architecture with SchottkyPlus technology-enabling Schottky-like reverse recovery performance (trr = 38.6 ns, Qr = 34 nC) while maintaining < 1 µA leakage at 25 °C. Its optimized gate charge profile (QGD = 8.5 nC at 4.5 V) minimizes switching losses in hard-switched topologies.
The device is rated for continuous drain current up to 100 A at Tmb = 25 °C, with junction temperature range from –55 °C to 175 °C and peak avalanche energy of 653 mJ under unclamped inductive switching. The clip-bonded, solder-die-attach construction eliminates wire bonds and glue, supporting wave soldering and 175 °C qualification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V maximum drain-source voltage - defines safe operating voltage ceiling in buck, boost, and OR-ing applications. |
| RDS(on) | 1.11 mΩ typical at VGS = 10 V, Tj = 25 °C - enables < 1.2 W conduction loss at 100 A, critical for POL and VRM efficiency. |
| QG(tot) | 27.6 nC at VGS = 4.5 V - supports fast turn-on with low gate driver power demand in high-frequency (>500 kHz) converters. |
| trr | 38.6 ns typical - reduces diode recovery loss and EMI in synchronous rectification and half-bridge configurations. |
| Rth(j-mb) | 0.81 K/W typical - allows direct thermal coupling to heatsink or copper plane, enabling >100 W dissipation with modest ΔT. |
| ID | 100 A continuous at Tmb = 25 °C - limited by package thermal capacity, not silicon, confirming LFPAK56's high-current capability. |
| EAS | 653 mJ non-repetitive avalanche energy - provides robustness against inductive switching transients without external snubbers. |
Pinout & Package
LFPAK56 (SOT669) is a leadless, clip-bonded surface-mount package with exposed mounting base connected to drain, optimized for low parasitic inductance and high thermal conductivity. It features wave-solderable leads and visual solder inspection capability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three parallel source terminals reduce source inductance and improve current sharing in high-di/dt switching. |
| 4 | Gate (G) | Single gate input with low RG (1.1 Ω) - ensures stable drive and minimal gate oscillation in high-speed operation. |
| Mounting Base | Drain (D) | Exposed copper pad electrically and thermally connected to drain - serves as primary heat path and high-current return node. |
Key Features
| Feature | Design Value |
|---|---|
| SchottkyPlus body diode | Soft reverse recovery (s-factor = 0.99) with < 1 µA leakage at 25 °C - eliminates trade-off between low Qr and high leakage in conventional MOSFETs. |
| Ultra-low QG/QGD | 27.6 nC total gate charge and 8.5 nC gate-drain charge at 4.5 V - enables efficient 4.5 V logic-level drive and reduces Miller-induced shoot-through risk. |
| Clip-bonded construction | No wire bonds or die attach glue - achieves 175 °C qualification and superior power cycling reliability vs. standard SO-8. |
| Low parasitic inductance | Optimized internal layout and triple-source configuration - suppresses voltage spikes and ringing during hard switching. |
| Wave solderable leads | Exposed coplanar leads - enable automated optical inspection and eliminate voiding concerns common in thermal-pad-only packages. |
Applications
| Server DC-DC Conversion | Telecom Secondary-Side Rectification |
|---|---|
|
Use Scenario: High-density 12 V–to–1 V point-of-load conversion in rack-mounted servers. IC Role / Device Role / Timing Role: Primary synchronous rectifier in multiphase buck converter, switching at 600–800 kHz. Use Value: 1.11 mΩ RDS(on) and 38.6 ns trr reduce conduction + recovery losses by >15% vs. legacy MOSFETs, improving system efficiency at 40–60 A per phase. |
Use Scenario: Secondary-side synchronous rectification in 48 V–to–12 V isolated DC-DC modules for telecom base stations. IC Role / Device Role / Timing Role: Low-side switch replacing Schottky diodes in forward or LLC resonant converters. Use Value: SchottkyPlus diode delivers < 0.8 V VSD and soft recovery, cutting diode conduction loss by ~40% and eliminating snubber components. |
| VRM Power Delivery | Power OR-ing |
|
Use Scenario: Voltage regulator module supplying GPU and ASIC cores in AI accelerators. IC Role / Device Role / Timing Role: High-current, low-RDS(on) power stage switch operating with 3.3 V or 5 V gate drive. Use Value: 100 A continuous rating and 0.81 K/W Rth(j-mb) support >300 W per phase without forced air, enabling compact VRM designs. |
Use Scenario: Redundant 12 V power rail combining in enterprise storage controllers. IC Role / Device Role / Timing Role: Back-to-back configured MOSFET acting as ideal diode for hot-swap and fault isolation. Use Value: Ultra-low RDS(on) minimizes forward voltage drop (< 10 mV at 50 A), reducing power loss and thermal stress vs. discrete diode solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSMN2R0-30YLC | Higher RDS(on) (2.0 mΩ typ. at 10 V), same LFPAK56 package and SchottkyPlus diode. | Better suited for cost-sensitive, lower-current (< 60 A) POL modules where marginally higher loss is acceptable. | Select when thermal budget allows higher on-resistance and gate charge is secondary to BOM cost. |
| IRLHS6342 | SO-8 package (not LFPAK56), 1.7 mΩ RDS(on), no SchottkyPlus diode (trr = 65 ns, Qr = 62 nC). | Limited to < 50 A continuous due to higher Rth(j-a); unsuitable for high-frequency synchronous rectification. | Choose only if legacy SO-8 footprint must be retained and soft recovery is not required. |
Compared with PSMN2R0-30YLC, PSMN1R4-30YLD delivers 30% lower conduction loss and faster switching, justifying its use in high-power density designs; versus IRLHS6342, it offers superior thermal performance, lower EMI, and integrated soft-recovery-making it the preferred choice for next-gen telecom and server power stages.
Availability
PSMN1R4-30YLD is available at Aetrix Electronics and suitable for server DC-DC conversion, telecom secondary-side rectification, and VRM power delivery requiring stable component supply across industrial and datacenter production programs.
Supply support for PSMN1R4-30YLD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential semiconductors, delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and computing markets.
This device belongs to the NextPowerS3 portfolio, engineered specifically for high-efficiency, high-frequency power conversion in server, telecom, and AI infrastructure where low RDS(on), soft-recovery, and thermal robustness are critical.
FAQ
What gate drive voltage is required for full enhancement?
PSMN1R4-30YLD is specified as a logic-level MOSFET with VGS(th) of 1.2–2.2 V and is fully enhanced at VGS = 4.5 V, delivering RDS(on) = 1.44 mΩ (typ.) at 25 °C. At 10 V, RDS(on) drops to 1.11 mΩ (typ.), but 4.5 V drive is sufficient for most high-efficiency applications including VRMs and POL converters.
How does the SchottkyPlus body diode differ from a standard MOSFET body diode?
The SchottkyPlus diode achieves soft reverse recovery (s-factor = 0.99) and low Qr (34 nC) without elevated leakage-delivering < 1 µA IDSS at 25 °C. Unlike conventional body diodes or integrated Schottky diodes, it avoids the high leakage penalty while matching Schottky-like trr (38.6 ns) and VSD (~0.79 V).
Can PSMN1R4-30YLD be used in avalanche conditions?
Yes-it is 100% tested for non-repetitive avalanche energy (EAS) up to 653 mJ at Tj(init) = 25 °C, with VDS ≤ 30 V and ID = 25 A. This ruggedness supports reliable operation in inductive switching circuits such as OR-ing and motor control without external clamping.
Is the LFPAK56 package compatible with standard SO-8 reflow profiles?
Yes-the LFPAK56 (SOT669) package is qualified for standard lead-free reflow (JEDEC J-STD-020) and wave soldering. Its exposed mounting base and coplanar leads support both processes, and the absence of wire bonds eliminates mechanical stress risks during thermal cycling.
PSMN1R4-30YLD/2X Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SC-100, SOT-669
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 100A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 1.42mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 2.2V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 54.8 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 3840 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 166W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56, Power-SO8
PSMN1R4-30YLD/2X FAQ
1.How can I place an order for PSMN1R4-30YLD/2X through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN1R4-30YLD/2X on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN1R4-30YLD/2X reliable?
The price and inventory of PSMN1R4-30YLD/2X are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R4-30YLD/2X is usually 5 days.
3.What payment methods are accepted for PSMN1R4-30YLD/2X?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN1R4-30YLD/2X transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN1R4-30YLD/2X?
PSMN1R4-30YLD/2X orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN1R4-30YLD/2X order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN1R4-30YLD/2X?
For technical support, including PSMN1R4-30YLD/2X datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R4-30YLD/2X requirements.
6.How does Aetrix verify that PSMN1R4-30YLD/2X is sourced from the original manufacturer or authorized distributors?
All PSMN1R4-30YLD/2X products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R4-30YLD/2X meets industry standards.
7.What is the process for return or replacement of PSMN1R4-30YLD/2X?
All PSMN1R4-30YLD/2X units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R4-30YLD/2X, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN1R4-30YLD/2X part is unused and in its original packaging.
Return procedure for PSMN1R4-30YLD/2X:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PSMN1R4-30YLD/2X Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

