Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Nexperia USA Inc. PSMN1R6-40YLC,115

Name: PSMN1R6-40YLC,115
Brand: Nexperia USA Inc.
SKU: PSMN1R6-40YLC,115
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: PSMN1R6-40YLC,115

Manufacturer:: Nexperia USA Inc.

Category:: FETs, MOSFETs

Package:: SOT-1023, 4-LFPAK

Datasheet:: PSMN1R6-40YLC,115.pdf

Description:: MOSFET N-CH 40V 100A LFPAK56

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:5,508

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

PSMN1R6-40YLC from Nexperia is an N-channel logic-level enhancement-mode MOSFET in LFPAK (SOT1023) package, rated for 40 V V_DS, 1.55 mΩ R_DS(on) at V_GS = 10 V and T_j = 25 °C, with 100 A continuous drain current capability at T_mb = 25 °C. It employs NextPower Superjunction technology optimized for 4.5 V gate drive and is used in high-efficiency DC-DC converters and server power supplies.

For engineers reviewing the PSMN1R6-40YLC datasheet, PSMN1R6-40YLC pinout, PSMN1R6-40YLC application, or PSMN1R6-40YLC equivalent, key selection criteria include its ultra-low R_DS(on) and Q_G/Q_GD, thermal resistance of 0.35 K/W (j-mb), and LFPAK mounting base configuration enabling high-power density board layouts.

Technical Context

This MOSFET uses NextPower Superjunction architecture to achieve low conduction and switching losses simultaneously. Its gate threshold voltage (V_GS(th)) ranges from 1.05 V to 1.95 V at 25 °C, ensuring reliable turn-on with 4.5 V logic-level drive while maintaining low leakage (I_DSS ≤ 1 µA at 25 °C).

The device integrates a robust source-drain diode with V_SD = 0.77 V at I_S = 25 A and T_j = 25 °C, and supports unclamped avalanche energy up to 391 mJ. Thermal design is enabled by direct-mounting via the exposed drain-connected mounting base (mb), delivering R_th(j-mb) = 0.35 K/W typical.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	40 V - Maximum drain-source blocking voltage; defines use in ≤40 V bus systems like 12 V/24 V/36 V server and telecom rails.
R_DS(on)	1.55 mΩ @ V_GS = 10 V, T_j = 25 °C - Enables <150 mW conduction loss at 100 A, critical for high-current sync rectification.
I_D (cont)	100 A @ T_mb = 25 °C - Continuous current rating limited by package thermal capacity, not silicon die.
Q_G(tot)	59 nC @ V_GS = 4.5 V - Low total gate charge reduces driver power and enables fast switching with standard gate drivers.
R_th(j-mb)	0.35 K/W - Junction-to-mounting-base thermal resistance enables direct heatsink attachment without PCB vias, improving thermal reliability.
V_GS(th)	1.46 V typ @ T_j = 25 °C - Ensures full enhancement at 4.5 V logic levels, eliminating need for level-shifting gate drivers.
Q_GD	15.3 nC @ V_GS = 4.5 V - Low gate-drain charge minimizes Miller-induced switching delay and dv/dt-induced false turn-on.

Pinout & Package

LFPAK (SOT1023) is a plastic single-ended surface-mounted package with an exposed copper mounting base connected to the drain terminal. It provides low-inductance, high-current routing and superior thermal performance versus standard SO-8.

Pin/Terminal	Circuit Role	Design Meaning
1, 2, 3	Source (S)	Three parallel source terminals reduce source inductance and improve current sharing in high-frequency switching.
4	Gate (G)	Single gate input with RG = 1.17 Ω typical; designed for direct connection to standard logic-level PWM controllers.
mb	Mounting Base / Drain (D)	Exposed copper pad electrically connected to drain; serves as primary thermal path and high-current drain return.

Key Features

Feature	Design Value
NextPower Superjunction technology	Enables simultaneous optimization of R_DS(on) and Q_G, achieving 1.55 mΩ and 59 nC at 4.5 V drive - critical for high-efficiency 500 kHz+ DC-DC stages.
Ultra-low Q_GD and Q_OSS	15.3 nC Q_GD and 38.7 nC Q_OSS minimize switching losses and improve light-load efficiency in synchronous buck converters.
150 °C qualified Power-SO8 package	LFPAK construction passes industrial temperature qualification (T_j = −55 to +150 °C), supporting operation in sealed server chassis.
Low parasitic inductance layout	Three-source-pin configuration and integrated mounting base reduce loop inductance below 1.5 nH - suppresses voltage overshoot during hard switching.
Robust avalanche capability	391 mJ non-repetitive E_AS allows safe operation under inductive load switching transients without external snubbers.

Applications

DC-DC Converters

Server Power Supplies

Use Scenario: Primary-side switch in 48 V–12 V intermediate bus converters operating at 300–600 kHz.

IC Role / Device Role: High-side synchronous rectifier MOSFET replacing Schottky diodes to reduce conduction loss.

Use Value: Achieves >96% efficiency at 100 A output due to 1.55 mΩ R_DS(on) and low Q_G, reducing thermal load on VRMs.

Use Scenario: 12 V output rail regulation in dual-processor rack servers with dynamic load steps up to 100 A/µs.

IC Role / Device Role: Low-side switch in multiphase buck converters with integrated power stages.

Use Value: Three-source terminals and 0.35 K/W R_th(j-mb) enable stable operation under transient loads without thermal throttling.

Power OR-ing

Load Switching

Use Scenario: Redundant 12 V supply combining in telecom shelf systems using ideal diode controllers.

IC Role / Device Role: Back-to-back configured MOSFET for reverse-current blocking and low forward drop.

Use Value: V_GS(th) = 1.46 V ensures fast turn-on with controller bias, while R_DS(on) < 2 mΩ limits voltage drop to <200 mV at 100 A.

Use Scenario: Hot-swap protection and inrush limiting for PCIe add-in cards and NVMe SSD modules.

IC Role / Device Role: Single N-channel high-side load switch controlled via dedicated gate driver IC.

Use Value: 40 V rating and 1304 A peak drain current support robust fault clearing during short-circuit events.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Infineon IPP026N04L	R_DS(on) = 2.6 mΩ @ 4.5 V; Q_G = 47 nC; TO-252 package	Higher R_DS(on) increases conduction loss by ~65 % at 100 A; larger footprint and higher R_th(j-case).	Prefer when cost sensitivity outweighs efficiency and board space constraints.
Vishay SiR872DP	R_DS(on) = 1.4 mΩ @ 10 V; Q_G = 72 nC; PowerPAK SO-8	Higher Q_G increases switching loss; no mounting base - relies on PCB copper for thermal dissipation.	Prefer when gate drive strength is sufficient and thermal interface to heatsink is not required.

Compared with PSMN1R6-40YLC, IPP026N04L trades lower gate charge for higher on-resistance and inferior thermal path, while SiR872DP offers marginally lower R_DS(on) but lacks the integrated mounting base and suffers from higher switching loss due to greater Q_G.

Availability

PSMN1R6-40YLC is available at Aetrix Electronics and suitable for server power supplies, DC-DC converters, and power OR-ing applications requiring stable component supply across multi-year production cycles.

Supply support for PSMN1R6-40YLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete, logic, and MOSFET solutions, with manufacturing and R&D centers across Asia, Europe, and the US.

This device belongs to Nexperia's NextPower Superjunction MOSFET product line, engineered specifically for high-efficiency, high-current power conversion in datacenter, telecom, and industrial infrastructure.

FAQ

What is the maximum continuous drain current for PSMN1R6-40YLC at 100 °C mounting base temperature?

At T_mb = 100 °C, the continuous drain current is 100 A - identical to the rating at 25 °C - because current limitation is package-defined and derating begins only above 100 °C per Figure 1 in the datasheet. This reflects the robust thermal design of the LFPAK mounting base.

Does PSMN1R6-40YLC require a gate resistor for stability in high-speed switching?

A gate resistor of 4.7 Ω is recommended (per Figure 4 test conditions) to dampen ringing caused by low gate-drain capacitance and high dV/dt. The device's intrinsic gate resistance is 1.17 Ω, so external series resistance controls turn-on/turn-off slew rate and prevents oscillation with common PWM controllers.

Can PSMN1R6-40YLC be used in avalanche mode for inductive load switching?

Yes - it is rated for 391 mJ non-repetitive drain-source avalanche energy (E_AS) under specified conditions (V_GS = 10 V, I_D = 100 A, V_sup ≤ 40 V). This enables safe operation during inductive turn-off transients without external clamping, provided single-pulse timing and junction temperature remain within limits.

How does the LFPAK package improve thermal performance over standard SO-8?

The LFPAK exposes the drain-connected mounting base (mb) as a large copper area directly soldered to the PCB or heatsink, achieving R_th(j-mb) = 0.35 K/W - nearly 3× better than SO-8's R_th(j-case). This eliminates reliance on PCB vias and reduces thermal impedance by bypassing epoxy mold compound and leadframe paths.

PSMN1R6-40YLC,115 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: -

Package/Case:: SOT-1023, 4-LFPAK

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 40 V

Current - Continuous Drain (Id) @ 25°C:: 100A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 4.5V, 10V

Rds On (Max) @ Id, Vgs:: 1.55mOhm @ 25A, 10V

Vgs(th) (Max) @ Id:: 1.95V @ 1mA

Gate Charge (Qg) (Max) @ Vgs:: 126 nC @ 10 V

Vgs (Max):: ±20V

Input Capacitance (Ciss) (Max) @ Vds:: 7790 pF @ 20 V

FET Feature:: -

Power Dissipation (Max):: 288W (Tc)

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: LFPAK56; Power-SO8

PSMN1R6-40YLC,115 FAQ

1.How can I place an order for PSMN1R6-40YLC,115 through Aetrix?

Please submit a Request for Quotation (RFQ) for PSMN1R6-40YLC,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PSMN1R6-40YLC,115 reliable?

The price and inventory of PSMN1R6-40YLC,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R6-40YLC,115 is usually 5 days.

3.What payment methods are accepted for PSMN1R6-40YLC,115?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN1R6-40YLC,115 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PSMN1R6-40YLC,115?

PSMN1R6-40YLC,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PSMN1R6-40YLC,115 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PSMN1R6-40YLC,115?

For technical support, including PSMN1R6-40YLC,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R6-40YLC,115 requirements.

6.How does Aetrix verify that PSMN1R6-40YLC,115 is sourced from the original manufacturer or authorized distributors?

All PSMN1R6-40YLC,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R6-40YLC,115 meets industry standards.

7.What is the process for return or replacement of PSMN1R6-40YLC,115?

All PSMN1R6-40YLC,115 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R6-40YLC,115, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PSMN1R6-40YLC,115 part is unused and in its original packaging.

Return procedure for PSMN1R6-40YLC,115:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…