Nexperia USA Inc. PSMN1R6-40YLC:115
- Part No.:
- PSMN1R6-40YLC:115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SOT-1023, 4-LFPAK
- Datasheet:
-
PSMN1R6-40YLC:115.pdf
- Description:
- MOSFET N-CH 40V 100A LFPAK56
- Quantity:
- Payment:

- Shipping:

Inventory:7,937
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Product details
Overview
PSMN1R6-40YLC from Nexperia is a logic-level N-channel enhancement-mode MOSFET in LFPAK (SOT1023) package, rated for 40 V VDS, 1.55 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C, with 100 A continuous drain current at Tmb = 25 °C and ultra-low QG (59 nC at 4.5 V). It serves as a high-efficiency power switch in synchronous rectification and DC-DC converter primary/secondary side switching.
For engineers reviewing the PSMN1R6-40YLC datasheet, PSMN1R6-40YLC pinout, PSMN1R6-40YLC application, or PSMN1R6-40YLC equivalent, key selection criteria include gate drive compatibility at 4.5 V, thermal resistance to mounting base (0.35 K/W typ), avalanche ruggedness (391 mJ), low parasitic inductance, and LFPAK package suitability for high-current PCB layouts.
Technical Context
This MOSFET employs Nexperia's NextPower Superjunction technology to achieve ultra-low RDS(on) and optimized dynamic charge parameters-QGD = 15.3 nC and QOSS = 38.7 nC at VGS = 4.5 V-enabling high-frequency switching with minimal conduction and switching losses. Its gate threshold voltage (VGS(th)) ranges from 1.05 V to 1.95 V at 25 °C, ensuring reliable turn-on with standard logic-level drivers.
The device features an integrated source-drain diode with VSD = 0.77 V at IS = 25 A and Tj = 25 °C, and supports unclamped inductive switching with EAS = 391 mJ at ID = 100 A. Thermal design is enabled by direct die-to-mounting-base conduction path, yielding Rth(j-mb) = 0.35 K/W typical.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 40 V - Maximum blocking voltage for 12 V/24 V/36 V input systems and 48 V intermediate bus applications. |
| RDS(on) | 1.55 mΩ @ VGS = 10 V, Tj = 25 °C - Enables <1.5 W conduction loss at 60 A, critical for high-current server VRMs. |
| ID (cont) | 100 A @ Tmb = 25 °C - Sustained current capability limited by LFPAK thermal interface, not silicon. |
| QG(tot) | 59 nC @ VGS = 4.5 V - Low gate charge reduces driver power and enables efficient 500 kHz–1 MHz operation. |
| Rth(j-mb) | 0.35 K/W typ - Enables direct heatsinking to copper planes or external heatsinks without thermal vias. |
| EAS | 391 mJ - Robust unclamped avalanche rating supports reliable operation in hard-switched topologies. |
| Ciss | 7790 pF - High input capacitance mitigates EMI but requires careful gate driver sizing for fast transitions. |
Pinout & Package
LFPAK (SOT1023) is a 4-lead plastic single-ended surface-mounted package with exposed mounting base connected to drain. Its low-profile, high-copper-content construction delivers superior thermal and current-handling performance versus standard SO-8.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 (S) | Source | Three parallel source terminals minimize source inductance and improve current sharing in high-di/dt applications. |
| 4 (G) | Gate | Single gate terminal with RG = 1.17 Ω typ - enables stable switching with moderate gate resistance (4.7 Ω typical). |
| Mounting Base (mb) | Drain | Exposed copper pad electrically and thermally connected to drain - provides primary heat path and high-current return path. |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level gate drive | Guaranteed turn-on at VGS = 4.5 V - compatible with 3.3 V and 5 V microcontrollers and PWM controllers without level-shifting. |
| NextPower Superjunction architecture | Reduces RDS(on) × QG figure-of-merit by >30% vs. planar MOSFETs - improves efficiency across light-to-heavy load conditions. |
| Ultra-low QGD/QOSS | QGD = 15.3 nC, QOSS = 38.7 nC - minimizes Miller-induced switching delay and output energy loss during hard switching. |
| High-reliability Power-SO8 qualification | Qualified to 150 °C junction temperature - supports extended lifetime in industrial and telecom power supplies. |
| Low parasitic inductance | Optimized internal layout and triple-source leads - reduces voltage overshoot and ringing in synchronous buck converters. |
Applications
| Server Power Supply VRM | Synchronous Rectifier |
|---|---|
Use Scenario: High-density 48 V–12 V step-down conversion in AI accelerator racks with >600 A per phase. IC Role / Device Role / Timing Role: Primary-side high-side switch in multiphase buck converter operating at 600 kHz with 4.5 V gate drive. Use Value: 1.55 mΩ RDS(on) and 0.35 K/W Rth(j-mb) enable <95% efficiency at 50 A per phase while maintaining Tj < 110 °C. | Use Scenario: Secondary-side rectification in isolated LLC resonant converter for telecom rectifiers. IC Role / Device Role / Timing Role: Low-VF synchronous rectifier replacing Schottky diodes, driven by transformer-coupled gate signals. Use Value: VSD = 0.77 V and fast trr = 44 ns reduce conduction and reverse recovery losses by >40% vs. 40 V Schottky diodes. |
| DC-DC Converter for Industrial PLC | Power OR-ing Circuit |
Use Scenario: 24 V input to 5 V/3.3 V point-of-load regulation in programmable logic controller backplanes. IC Role / Device Role / Timing Role: High-side switch in compact 1 MHz buck converter with tight thermal constraints on multilayer PCB. Use Value: Triple-source configuration and low Lsource suppress voltage spikes during 100 A/µs di/dt transients, improving system reliability. | Use Scenario: Redundant 12 V power rail combining from dual hot-swap controllers in network switches. IC Role / Device Role / Timing Role: Low-RDS(on) OR-ing FET placed between supply and load, controlled by ideal diode controller. Use Value: 1.55 mΩ RDS(on) limits forward drop to <150 mV at 100 A, reducing power loss and thermal stress vs. discrete diode solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon IPP026N04L | RDS(on) = 2.6 mΩ @ 4.5 V; QG = 42 nC; TO-252 package | Higher RDS(on) increases conduction loss; larger package raises thermal resistance (Rth(j-a) ≈ 45 K/W) | Prefer when cost sensitivity outweighs efficiency and board space constraints. |
| Vishay SiR872DP | RDS(on) = 1.45 mΩ @ 10 V; QG = 62 nC; PowerPAK SO-8 | Similar RDS(on) but higher QG; no specified avalanche rating | Consider where gate drive strength is ample and avalanche robustness is non-critical. |
Compared with IPP026N04L and SiR872DP, PSMN1R6-40YLC offers the lowest RDS(on) × QG product (91 fJ), best thermal path via mounting base, and verified 391 mJ avalanche capability-making it optimal for high-efficiency, high-reliability, space-constrained power stages.
Availability
PSMN1R6-40YLC is available at Aetrix Electronics and suitable for server power supplies, synchronous rectifiers, and industrial DC-DC converters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for PSMN1R6-40YLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential semiconductors - high-volume, high-reliability devices for automotive, industrial, and consumer applications.
This part belongs to Nexperia's NextPower logic-level MOSFET product line, engineered for high-efficiency, high-current switching in compact power supplies where low RDS(on), fast switching, and robust thermal performance are critical.
FAQ
What is the maximum continuous drain current for PSMN1R6-40YLC at 100 °C mounting base temperature?
At Tmb = 100 °C, the continuous drain current remains 100 A per Figure 1 of the datasheet. This reflects the package-limited rating - the LFPAK construction maintains current capacity up to 100 °C mounting temperature before derating begins, unlike conventional SO-8 packages that derate significantly above 70 °C.
Does PSMN1R6-40YLC have an integrated body diode, and what are its key characteristics?
Yes, it includes a source-drain diode with VSD = 0.77 V at IS = 25 A and Tj = 25 °C, reverse recovery time trr = 44 ns, and recovered charge Qr = 62 nC. These values confirm suitability for synchronous rectification where low forward voltage and fast recovery minimize losses compared to discrete Schottky diodes.
Can PSMN1R6-40YLC be used with 3.3 V gate drive in high-current applications?
No - while VGS(th) starts at ~1.05 V, RDS(on) rises sharply below 4.5 V. At VGS = 3.3 V, RDS(on) exceeds 4 mΩ (per Fig. 7), doubling conduction loss. The device is optimized for 4.5 V minimum gate drive; use only with 3.3 V logic if paired with gate boosting or level-shifting circuitry.
How does the LFPAK package improve thermal performance over standard SO-8?
The LFPAK (SOT1023) exposes the drain-connected mounting base directly to the PCB, achieving Rth(j-mb) = 0.35 K/W - over 5× better than SO-8's typical Rth(j-a) of 2.5 K/W. This allows >80% of heat to exit through the copper plane, enabling higher sustained current without heatsinks in space-constrained designs.
PSMN1R6-40YLC:115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SOT-1023, 4-LFPAK
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 40 V
- Current - Continuous Drain (Id) @ 25°C:
- 100A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 1.55mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 1.95V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 126 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 7790 pF @ 20 V
- FET Feature:
- -
- Power Dissipation (Max):
- 288W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56; Power-SO8
PSMN1R6-40YLC:115 FAQ
1.How can I place an order for PSMN1R6-40YLC:115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN1R6-40YLC:115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN1R6-40YLC:115 reliable?
The price and inventory of PSMN1R6-40YLC:115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN1R6-40YLC:115 is usually 5 days.
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Once your PSMN1R6-40YLC:115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN1R6-40YLC:115?
For technical support, including PSMN1R6-40YLC:115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN1R6-40YLC:115 requirements.
6.How does Aetrix verify that PSMN1R6-40YLC:115 is sourced from the original manufacturer or authorized distributors?
All PSMN1R6-40YLC:115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN1R6-40YLC:115 meets industry standards.
7.What is the process for return or replacement of PSMN1R6-40YLC:115?
All PSMN1R6-40YLC:115 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN1R6-40YLC:115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN1R6-40YLC:115 part is unused and in its original packaging.
Return procedure for PSMN1R6-40YLC:115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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