Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Nexperia USA Inc. PSMN2R0-100SSFJ

Name: PSMN2R0-100SSFJ
Brand: Nexperia USA Inc.
SKU: PSMN2R0-100SSFJ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: PSMN2R0-100SSFJ

Manufacturer:: Nexperia USA Inc.

Category:: FETs, MOSFETs

Package:: SOT-1235

Datasheet:: PSMN2R0-100SSFJ.pdf

Description:: NEXTPOWER 80/100V MOSFETS

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,754

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

PSMN2R0-100SSF from Nexperia is a 100 V, N-channel enhancement-mode MOSFET in LFPAK88 (SOT1235) package, rated for 267 A continuous drain current at T_mb = 25 °C, with typ. R_DS(on) = 1.63 mΩ at V_GS = 10 V and T_j = 25 °C. It features low Q_GD (31 nC typ.), strong avalanche ruggedness (732 mJ), and is qualified to 175 °C junction temperature - deployed as primary-side switch and synchronous rectifier in high-efficiency industrial DC-DC converters.

For engineers reviewing the PSMN2R0-100SSF datasheet, PSMN2R0-100SSF pinout, PSMN2R0-100SSF application, or PSMN2R0-100SSF equivalent, key selection criteria include R_DS(on) vs. temperature stability, gate charge profile for hard-switching efficiency, thermal resistance to mounting base (R_th(j-mb) = 0.2 K/W typ.), and avalanche energy rating under unclamped inductive switching.

Technical Context

This MOSFET employs a trench-gate superjunction structure optimized for low conduction and switching losses in high-current, high-frequency power conversion. Its gate threshold voltage (V_GS(th)) ranges 2–4 V at 25 °C and exhibits -8.8 mV/K temperature coefficient, enabling stable turn-on behavior across -55 to 175 °C operation.

The device integrates a robust body diode with 55 nC recovered charge (Q_r) and 54 ns reverse recovery time (t_rr), supporting synchronous rectification without external Schottky assistance. The LFPAK88 package delivers 0.2 K/W typical junction-to-mounting-base thermal resistance, enabling high-power density designs on standard PCB copper areas.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	100 V - Maximum blocking voltage for primary-side switch in 48 V–96 V bus systems
R_DS(on) (typ.)	1.63 mΩ at V_GS = 10 V, T_j = 25 °C - Enables <1.7 W conduction loss at 250 A
I_D (cont.)	267 A at T_mb = 25 °C - Validated continuous current with proper heatsinking and PCB copper area
Q_G(tot) (typ.)	161 nC - Determines gate driver power requirement and switching speed in 100–500 kHz converters
E_AS	732 mJ - Supports single-pulse unclamped inductive switching up to 82 A without failure
R_th(j-mb) (typ.)	0.2 K/W - Allows direct thermal coupling to heatsink or copper plane, critical for >200 W dissipation
t_rr	54 ns - Minimizes diode reverse recovery loss in synchronous rectifier mode

Pinout & Package

LFPAK88 (SOT1235) is a 4-lead, single-ended surface-mount package with 8 mm × 8 mm × 1.6 mm body, featuring an exposed mounting base electrically connected to the drain terminal for optimal thermal and electrical performance.

Pin/Terminal	Circuit Role	Design Meaning
1	G	Gate input - Controls channel conduction; requires low-inductance layout due to 161 nC total gate charge
2	S	Source - Common reference node for gate drive and current sensing; tied to three internal source bonds
3	S	Source - Redundant source connection to reduce bondwire inductance and improve current sharing
4	S	Source - Third parallel source terminal enhancing low-impedance return path for high di/dt switching
mb	D	Mounting base (drain) - Primary thermal path and high-current drain connection; soldered directly to PCB copper

Key Features

Feature	Design Value
Low Q_rr (55 nC)	Reduces diode recovery loss and EMI in synchronous rectifier topologies
Strong avalanche rating (732 mJ)	Enables reliable operation in hard-switched flyback and resonant converters without snubbers
100% avalanche tested	Guarantees ruggedness per unit - no statistical screening required in safety-critical power stages
LFPAK88 RoHS-compliant package	Supports lead-free reflow (260 °C peak) and achieves 0.2 K/W thermal resistance without thermal vias
Q_G × R_DS(on) FOM = 262 Ω·nC (typ.)	Optimized trade-off for high-efficiency, high-frequency SMPS designs above 200 kHz

Applications

AC-DC Server PSU

Industrial BLDC Inverter

Use Scenario: Primary-side switch in 3.3 kW LLC resonant converter for AI server power supply.

IC Role / Device Role / Timing Role: High-side main switch operating at 300–500 kHz with zero-voltage switching (ZVS).

Use Value: 1.63 mΩ R_DS(on) minimizes conduction loss at 200+ A peak current; low Q_GD ensures clean ZVS transition and reduces gate drive loss.

Use Scenario: Phase-leg high-side switch in 15 kW industrial BLDC motor drive with 120° commutation.

IC Role / Device Role / Timing Role: Fast-turning N-channel switch handling 250 A phase current with <100 ns dead-time constraints.

Use Value: 54 ns t_rr and 55 nC Q_r prevent shoot-through during freewheeling; 175 °C rating supports compact heatsink design in enclosed enclosures.

Telecom DC-DC Brick

Battery Protection Module

Use Scenario: Synchronous rectifier in 48 V input, 12 V/300 A output telecom brick using multiphase buck topology.

IC Role / Device Role / Timing Role: Low-side synchronous rectifier with forced commutation and adaptive gate timing.

Use Value: 0.8 V V_SD forward drop at 25 A reduces conduction loss by 40% vs. discrete Schottky; low R_DS(on) enables bidirectional current capability.

Use Scenario: Main discharge FET in 72 V Li-ion battery pack protection circuit with overcurrent and short-circuit cutoff.

IC Role / Device Role / Timing Role: High-current, low-R_DS(on) pass element activated by protection IC during normal operation.

Use Value: 267 A continuous rating supports 300 A burst load; 732 mJ E_AS withstands inductive kick during fast fault shutdown without destruction.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current, 100 V N-channel MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Infineon IPP020N10N5	R_DS(on) = 2.0 mΩ (typ.), Q_G(tot) = 150 nC, TO-220FP package	Higher thermal resistance (R_th(j-c) ≈ 0.8 K/W); requires mechanical heatsink	Preferred where through-hole assembly or legacy footprint compatibility is required
Vishay SiR626DP	R_DS(on) = 1.85 mΩ (typ.), Q_G(tot) = 172 nC, PowerPAK 8x8 package	Higher Q_G increases gate drive loss; no 100% avalanche test guarantee	Selected when higher gate charge tolerance is acceptable and LFPAK88 footprint is not mandatory

Compared with IPP020N10N5 and SiR626DP, PSMN2R0-100SSF offers superior thermal performance via its mounting-base architecture and guaranteed avalanche ruggedness - making it optimal for space-constrained, high-reliability industrial power stages where thermal management and fault robustness are prioritized over gate drive simplicity.

Availability

PSMN2R0-100SSF is available at Aetrix Electronics and suitable for AC-DC server PSUs, industrial BLDC inverters, and battery protection modules requiring stable component supply, long-term lifecycle support, and traceable sourcing for high-volume production.

Supply support for PSMN2R0-100SSF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors, delivering high-performance, reliable discrete and logic devices for power management, signal integrity, and interface applications.

This device belongs to the NextPower family - engineered for high-efficiency, high-current switching in industrial, telecom, and computing power supplies, emphasizing ruggedness, thermal performance, and system-level reliability over cost-optimized consumer-grade alternatives.

FAQ

What is the maximum continuous drain current at 100 °C mounting base temperature?

At T_mb = 100 °C, the continuous drain current is derated to 189 A (per Table 5 Limiting Values). This reflects thermal limitations of the LFPAK88 package under real-world PCB thermal conditions - not a device failure point, but the safe operational ceiling for sustained conduction without active cooling.

Is the mounting base (drain) electrically isolated from the PCB copper?

No - the mounting base is internally connected to the drain terminal and must be soldered directly to a PCB copper pour or heatsink. Electrical isolation requires insulating thermal interface material and careful layout to avoid unintended drain-to-ground shorts; the base is not dielectric-coated.

Does the 100% avalanche test apply to all production units?

Yes - every PSMN2R0-100SSF unit undergoes 100% unclamped inductive switching test at I_AS = 82 A and E_AS = 732 mJ per datasheet Figure 4. This is a production-screening requirement, not a sampling test, ensuring full-batch ruggedness compliance.

Can this MOSFET be used in paralleled configurations?

Yes - its positive temperature coefficient of R_DS(on) (normalized factor rises with T_j, Fig. 12) enables inherent current sharing. Successful parallel operation requires matched gate drive impedance, symmetrical PCB layout, and shared source routing to minimize dynamic imbalance - verified in Nexperia application note AN11158.

PSMN2R0-100SSFJ Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: -

Package/Case:: SOT-1235

Packaging:: Tape & Reel (TR)

Product Status:: Active

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 100 V

Current - Continuous Drain (Id) @ 25°C:: 267A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 7V, 10V

Rds On (Max) @ Id, Vgs:: 2.07mOhm @ 25A, 10V

Vgs(th) (Max) @ Id:: 4V @ 1mA

Gate Charge (Qg) (Max) @ Vgs:: 242 nC @ 10 V

Vgs (Max):: ±20V

Input Capacitance (Ciss) (Max) @ Vds:: 16140 pF @ 50 V

FET Feature:: -

Power Dissipation (Max):: 341W (Tc)

Operating Temperature:: -55°C ~ 175°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: LFPAK88 (SOT1235)

PSMN2R0-100SSFJ FAQ

1.How can I place an order for PSMN2R0-100SSFJ through Aetrix?

Please submit a Request for Quotation (RFQ) for PSMN2R0-100SSFJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PSMN2R0-100SSFJ reliable?

The price and inventory of PSMN2R0-100SSFJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN2R0-100SSFJ is usually 5 days.

3.What payment methods are accepted for PSMN2R0-100SSFJ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN2R0-100SSFJ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PSMN2R0-100SSFJ?

PSMN2R0-100SSFJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PSMN2R0-100SSFJ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PSMN2R0-100SSFJ?

For technical support, including PSMN2R0-100SSFJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN2R0-100SSFJ requirements.

6.How does Aetrix verify that PSMN2R0-100SSFJ is sourced from the original manufacturer or authorized distributors?

All PSMN2R0-100SSFJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN2R0-100SSFJ meets industry standards.

7.What is the process for return or replacement of PSMN2R0-100SSFJ?

All PSMN2R0-100SSFJ units undergo pre-shipment inspection (PSI). If there is an issue with PSMN2R0-100SSFJ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PSMN2R0-100SSFJ part is unused and in its original packaging.

Return procedure for PSMN2R0-100SSFJ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…