Nexperia USA Inc. PSMN2R8-25MLC,115

Overview

PSMN2R8-25MLC from Nexperia is a logic-level enhancement-mode N-channel MOSFET in LFPAK33 (SOT1210) package, rated for 25 V V_DS, 2.8 mΩ R_DS(on) at V_GS = 10 V and 25 A, optimized for 4.5 V gate drive using NextPower Superjunction technology, and deployed in high-efficiency DC-to-DC converters and synchronous buck regulators.

For engineers reviewing the PSMN2R8-25MLC datasheet, PSMN2R8-25MLC pinout, PSMN2R8-25MLC application, or PSMN2R8-25MLC equivalent, this device delivers ultra-low Q_G (16.3 nC), Q_GD (3.9 nC), and Q_OSS (14.3 nC) to minimize switching losses in high-frequency power stages while maintaining robust avalanche energy rating (77 mJ) and thermal resistance (1.49 K/W).

Technical Context

This MOSFET employs NextPower Superjunction architecture to achieve low on-resistance with minimal gate charge, enabling high system efficiency across light and heavy loads. Its 4.5 V logic-level gate threshold (V_GS(th) = 1.74 V typ.) ensures full enhancement with standard microcontroller I/O, and its integrated source-drain diode supports synchronous rectification with t_rr = 21.3 ns and Q_r = 14.1 nC.

The LFPAK33 package provides low parasitic inductance and resistance via a copper-clip mounting base connected directly to drain, enabling high-current handling (70 A continuous, 536 A pulsed) and efficient heat transfer from junction to PCB via the exposed D-pad. Thermal resistance R_th(j-mb) is 1.49 K/W typical, supporting high-power density designs without forced cooling.

Key Specifications

Pinout & Package

LFPAK33 (SOT1210) is a surface-mount plastic package with an exposed copper mounting base (D-pad) thermally and electrically connected to drain, offering superior thermal performance and low-inductance layout versus SO-8 or DPAK.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.

Compared with IRLHS6342TRPBF and DMN3022LSD-13, PSMN2R8-25MLC uniquely balances 25 V rating, sub-3 mΩ on-resistance at 4.5 V, ultra-low gate charge, and LFPAK33's low-R_th(j-mb)-making it optimal for compact, high-current, high-efficiency buck and load-switch designs where thermal headroom and switching speed are critical.

Availability

PSMN2R8-25MLC is available at Aetrix Electronics and suitable for DC-to-DC converters, synchronous buck regulators, and industrial load switching requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for PSMN2R8-25MLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified and industrial-grade MOSFETs, ESD protection, and logic ICs.

This device belongs to Nexperia's NextPower Superjunction MOSFET product line, engineered specifically for high-efficiency, high-frequency power conversion in industrial, communications, and computing applications where low R_DS(on), low Q_G, and robust thermal performance are essential.

FAQ

What is the maximum continuous drain current for PSMN2R8-25MLC?

The maximum continuous drain current is 70 A at T_mb = 25 °C with V_GS = 10 V, limited by package thermal capability-not silicon. At T_mb = 100 °C, it remains 70 A per Figure 1, confirming robust thermal design of the LFPAK33 mounting base.

Does PSMN2R8-25MLC support 3.3 V gate drive?

No-it is specified for logic-level operation down to 4.5 V gate drive, with V_GS(th) = 1.45–2.15 V and guaranteed R_DS(on) at V_GS = 4.5 V. At 3.3 V, R_DS(on) rises significantly (>10 mΩ), increasing conduction loss and thermal stress; use only with ≥4.5 V gate voltage.

Is the mounting base electrically isolated?

No-the mounting base (mb) is internally connected to the drain terminal, as confirmed in Table 2 and Figure 17. It must be routed to the same net as the drain in PCB layout and cannot serve as a thermal pad without electrical isolation measures.

What is the safe operating area (SOA) limitation at 100 µs pulse width?

At t_p = 100 µs, the SOA curve (Figure 4) limits ID to ~120 A at V_DS = 10 V. This reflects single-pulse avalanche and thermal constraints-not repetitive operation-and assumes proper PCB copper area and ambient conditions per the datasheet test setup.