Nexperia USA Inc. PSMN2R9-30MLC,115
- Part No.:
- PSMN2R9-30MLC,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SOT-1210, 8-LFPAK33 (5-Lead)
- Datasheet:
-
PSMN2R9-30MLC,115.pdf
- Description:
- MOSFET N-CH 30V 70A LFPAK33
- Quantity:
- Payment:

- Shipping:

Inventory:754
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PSMN2R9-30MLC from Nexperia is a logic-level enhancement-mode N-channel MOSFET in LFPAK33 (SOT1210) package, designed for high-efficiency DC-to-DC conversion and load switching. It delivers 2.95 mΩ RDS(on) at VGS = 10 V and Tj = 25 °C, supports 70 A continuous drain current at Tmb = 25 °C, and features ultra-low QG (16.7 nC @ 4.5 V) and QGD (4.4 nC) for fast switching in synchronous buck regulators.
For engineers reviewing the PSMN2R9-30MLC datasheet, PSMN2R9-30MLC pinout, PSMN2R9-30MLC application, or PSMN2R9-30MLC equivalent, this device is selected for its low gate charge, 30 V VDS rating, LFPAK33 thermal performance, and optimized 4.5 V drive compatibility in industrial power supplies and communications infrastructure.
Technical Context
This MOSFET uses Nexperia's NextPower Superjunction technology to achieve ultra-low parasitic inductance and resistance while maintaining robust avalanche ruggedness (75 mJ unclamped). Its gate threshold voltage (1.45–2.15 V) and low RDS(on) temperature coefficient enable stable operation across -55 °C to 175 °C junction range.
The LFPAK33 package integrates a thermally enhanced mounting base connected directly to the drain, delivering Rth(j-mb) = 1.44 K/W and enabling high-power density designs without external heatsinking in many applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum drain-source blocking voltage for 24 V input rail systems with margin. |
| RDS(on) @ 4.5 V | 3.3 mΩ typ - Enables efficient 5 V/3.3 V gate drive in compact synchronous rectifiers. |
| RDS(on) @ 10 V | 2.45 mΩ typ - Delivers lowest conduction loss in 12 V gate-driven industrial converters. |
| QG(tot) @ 4.5 V | 16.7 nC - Reduces gate driver power loss and enables >1 MHz switching in high-frequency SMPS. |
| QGD | 4.4 nC - Minimizes Miller-induced switching delay and improves hard-switching robustness. |
| Rth(j-mb) | 1.44 K/W - Allows 91 W power dissipation with minimal thermal rise when mounted on PCB copper. |
| VGS(th) | 1.78 V typ - Ensures reliable turn-on with standard logic-level microcontrollers and PWM controllers. |
Pinout & Package
LFPAK33 (SOT1210) is a surface-mount plastic package with exposed mounting base for direct thermal coupling to PCB copper. The package features three parallel source terminals and one gate terminal, with drain internally connected to the mounting base.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three low-inductance source connections reduce common-source inductance in high-di/dt switching. |
| 4 | Gate (G) | Single gate input optimized for low-impedance drive; compatible with standard gate drivers. |
| Mounting Base | Drain (D) | Electrically and thermally connected to drain; requires PCB copper pour for thermal management and electrical return path. |
Key Features
| Feature | Design Value |
|---|---|
| NextPower Superjunction architecture | Enables 2.95 mΩ RDS(on) at 30 V while maintaining <4.4 nC QGD for high-speed efficiency. |
| Optimized 4.5 V gate drive | Guarantees full enhancement at logic-level voltages, eliminating need for level-shifting in MCU-controlled loads. |
| Ultra-low QOSS | 15.1 nC - Reduces turn-off energy loss and improves light-load efficiency in buck converters. |
| High avalanche energy rating | 75 mJ (unclamped) - Withstands inductive switching transients without derating in non-isolated DC-DC stages. |
| Low Ciss/Coss ratio | 2419 pF / 500 pF - Improves controllability during hard switching and reduces EMI generation. |
Applications
| DC-to-DC Converters | Load Switching |
|---|---|
|
Use Scenario: Point-of-load (POL) converter in telecom base station power modules converting 12 V to 3.3 V/1.8 V for FPGA and ASIC rails. IC Role / Device Role: Synchronous rectifier in high-frequency (500 kHz–1 MHz) buck stage. Use Value: 2.45 mΩ RDS(on) at 10 V drive minimizes conduction loss; 16.7 nC QG enables efficient high-frequency operation. |
Use Scenario: Hot-swap and inrush control for 24 V industrial I/O modules with 50 A peak load requirements. IC Role / Device Role: Low-side load switch with integrated thermal protection via PCB copper thermal mass. Use Value: 70 A continuous current rating at Tmb = 25 °C and 1.44 K/W Rth(j-mb) allow direct PCB thermal management without heatsink. |
| Synchronous Buck Regulator | Industrial Motor Drive Gate Driver Stage |
|
Use Scenario: Main output stage of isolated 48 V–12 V intermediate bus converter in programmable logic controller (PLC) power supply. IC Role / Device Role: High-side switch in dual-MOSFET synchronous buck topology. Use Value: 3.3 mΩ RDS(on) @ 4.5 V ensures full turn-on with standard 5 V gate drivers; low QGD suppresses shoot-through risk. |
Use Scenario: Half-bridge high-side switch in 24 V BLDC motor gate driver for factory automation actuators. IC Role / Device Role: Logic-level driven high-side FET with integrated source sensing for current monitoring. Use Value: Three-source-pin configuration enables Kelvin source connection for accurate current sensing; 175 °C max Tj supports sealed enclosure operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon IPP040N04L | 40 V VDS, 3.8 mΩ RDS(on) @ 4.5 V, TO-252 package, higher Rth(j-a). | Requires larger PCB area and less effective thermal coupling than LFPAK33 mounting base. | Choose when 40 V rating is mandatory and board space permits DPAK footprint. |
| ON Semiconductor NTMFS4C09NT1G | 30 V VDS, 3.2 mΩ RDS(on) @ 4.5 V, PowerTrench SO-8, no exposed drain pad. | Limited power handling (52 W) due to higher Rth(j-mb); unsuitable for >50 A continuous loads. | Choose only for space-constrained low-current (<30 A) applications where SO-8 is preferred. |
Compared with IPP040N04L and NTMFS4C09NT1G, PSMN2R9-30MLC offers superior thermal performance via LFPAK33 mounting base, lower QG for faster switching, and tighter RDS(on) tolerance-making it optimal for high-current, high-efficiency industrial DC-DC and load switching where thermal density matters.
Availability
PSMN2R9-30MLC is available at Aetrix Electronics and suitable for industrial power supplies, telecommunications infrastructure equipment, and domestic appliance motor control requiring stable component supply and long-term manufacturability.
Supply support for PSMN2R9-30MLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in MOSFETs, diodes, and ESD protection components.
This part belongs to Nexperia's NextPower Superjunction MOSFET product line, engineered specifically for high-efficiency, high-power-density switching applications in industrial and communications power systems.
FAQ
What is the maximum continuous drain current for PSMN2R9-30MLC at 100 °C mounting base temperature?
At Tmb = 100 °C, the continuous drain current remains 70 A per datasheet limiting values (Table 4), as current rating is not derated with mounting base temperature up to 100 °C. Derating begins above 100 °C per Figure 1, where ID drops to ~55 A at Tmb = 125 °C.
Can PSMN2R9-30MLC be used with 3.3 V gate drive in a synchronous buck converter?
No-while VGS(th) starts at 1.45 V, RDS(on) rises sharply below 4.5 V: at VGS = 3.3 V, RDS(on) exceeds 10 mΩ (extrapolated from Figure 7), causing excessive conduction loss. It is specified and optimized for ≥4.5 V gate drive.
Is the mounting base electrically isolated from the drain terminal?
No-the mounting base is internally connected to the drain (as confirmed in Table 2 pinning and Figure 17 package outline). It must be routed as a high-voltage node on the PCB and cannot serve as a ground or source reference plane.
Does PSMN2R9-30MLC have integrated ESD protection on the gate?
Yes-the datasheet specifies VESD = 340 V (MM method, JEDEC JESD22-A115), confirming built-in gate oxide protection sufficient for standard handling and board assembly, though external TVS is still recommended in high-noise industrial environments.
PSMN2R9-30MLC,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SOT-1210, 8-LFPAK33 (5-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 70A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 2.9mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 2.15V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 36.1 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 2419 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 91W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK33
PSMN2R9-30MLC,115 FAQ
1.How can I place an order for PSMN2R9-30MLC,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN2R9-30MLC,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN2R9-30MLC,115 reliable?
The price and inventory of PSMN2R9-30MLC,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN2R9-30MLC,115 is usually 5 days.
3.What payment methods are accepted for PSMN2R9-30MLC,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN2R9-30MLC,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN2R9-30MLC,115?
PSMN2R9-30MLC,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN2R9-30MLC,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN2R9-30MLC,115?
For technical support, including PSMN2R9-30MLC,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN2R9-30MLC,115 requirements.
6.How does Aetrix verify that PSMN2R9-30MLC,115 is sourced from the original manufacturer or authorized distributors?
All PSMN2R9-30MLC,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN2R9-30MLC,115 meets industry standards.
7.What is the process for return or replacement of PSMN2R9-30MLC,115?
All PSMN2R9-30MLC,115 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN2R9-30MLC,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN2R9-30MLC,115 part is unused and in its original packaging.
Return procedure for PSMN2R9-30MLC,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PSMN2R9-30MLC,115 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

