Nexperia USA Inc. PSMN3R9-25MLC,115
- Part No.:
- PSMN3R9-25MLC,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SOT-1210, 8-LFPAK33 (5-Lead)
- Datasheet:
-
PSMN3R9-25MLC,115.pdf
- Description:
- MOSFET N-CH 25V 70A LFPAK33
- Quantity:
- Payment:

- Shipping:

Inventory:1,513
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Product details
Overview
PSMN3R9-25MLC from Nexperia is a logic-level enhancement-mode N-channel MOSFET in LFPAK33 (SOT1210) package, rated for 25 V VDS, 4.15 mΩ RDS(on) at VGS = 10 V and 25 A, optimized for 4.5 V gate drive using NextPower Superjunction technology. It serves as a high-efficiency synchronous rectifier or load switch in compact DC-DC converters and buck regulators.
For engineers reviewing the PSMN3R9-25MLC datasheet, PSMN3R9-25MLC pinout, PSMN3R9-25MLC application, or PSMN3R9-25MLC equivalent, this device is selected for low-voltage, high-current switching where ultra-low QG (9.7 nC), QGD (2.3 nC), and thermal resistance (Rth(j-mb) = 1.95 K/W) directly impact system efficiency and thermal management in space-constrained industrial power stages.
Technical Context
This MOSFET employs Nexperia's NextPower Superjunction architecture to achieve ultra-low gate charge and on-resistance while maintaining robust avalanche ruggedness (EAS = 34.5 mJ). Its 4.5 V logic-level gate threshold (VGS(th) = 1.81 V typ) enables direct drive from 5 V or 3.3 V controllers without level shifting.
The LFPAK33 package integrates a thermally enhanced mounting base connected to the drain, enabling efficient heat transfer to PCB copper. The triple-source-pin configuration (Pins 1–3) reduces source inductance and improves switching stability in high-dI/dt applications like synchronous buck topologies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 25 V - Maximum drain-source blocking voltage; suitable for 12 V and 24 V input rails with margin. |
| RDS(on) | 4.15 mΩ @ VGS = 10 V, ID = 25 A, Tj = 25 °C - Enables <1 W conduction loss at 70 A continuous current under optimal thermal conditions. |
| QG(tot) | 9.7 nC @ VGS = 4.5 V - Reduces gate drive power and switching transition time, critical for >500 kHz DC-DC operation. |
| QGD | 2.3 nC - Minimizes Miller-induced turn-off delay and improves noise immunity during hard-switching. |
| Rth(j-mb) | 1.95 K/W - Junction-to-mounting-base thermal resistance enables >60 W power dissipation with moderate heatsinking on 2 oz copper. |
| ID | 70 A @ Tmb = 25 °C - Continuous drain current limited by package thermal capability, not silicon. |
| VGS(th) | 1.81 V typ - Ensures reliable turn-on with standard logic-level drivers; low temperature coefficient (−4.1 mV/K) maintains stability across −55 to 175 °C. |
Pinout & Package
LFPAK33 (SOT1210) is a surface-mount plastic package with exposed drain mounting base for superior thermal performance. Dimensions: 3.40 × 2.45 × 0.90 mm (L × W × H), with 4 signal leads and integrated thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 - S | Source | Three parallel source terminals reduce parasitic inductance and improve current sharing in high-frequency switching paths. |
| 4 - G | Gate | Single gate input; low gate resistance (RG = 1.8 Ω typ) supports fast, controlled turn-on/turn-off with minimal external gate resistor. |
| Mounting Base - D | Drain | Exposed copper drain pad soldered to PCB thermal plane; provides primary heat path and electrical connection to drain node. |
Key Features
| Feature | Design Value |
|---|---|
| NextPower Superjunction Technology | Enables 4.15 mΩ RDS(on) at 25 V rating while maintaining low QG and high avalanche energy (34.5 mJ). |
| Optimized for 4.5 V Gate Drive | VGS(th) = 1.81 V and low RDS(on) at 4.5 V (4.85 mΩ) allow direct interface with microcontrollers and PWM controllers without gate drivers. |
| Ultra-Low QGD and QOSS | QGD = 2.3 nC and QOSS = 9.9 nC minimize switching losses and improve light-load efficiency in buck converters. |
| Triple-Source Pin Configuration | Reduces source loop inductance by >30% vs. standard SO-8, suppressing voltage spikes and improving EMI in high-dI/dt synchronous rectification. |
| Robust Avalanche Rating | Non-repetitive EAS = 34.5 mJ at Tj = 25 °C ensures reliability during inductive load switching and fault transients. |
Applications
| DC-DC Converter Primary Switch | Synchronous Buck Regulator High-Side FET |
|---|---|
|
Use Scenario: 12 V input to 3.3 V/20 A output in telecom power module. IC Role / Device Role / Timing Role: High-side switching FET operating at 600 kHz with 4.5 V gate drive from controller IC. Use Value: 4.15 mΩ RDS(on) and 9.7 nC QG enable >95% peak efficiency and <15 ns rise/fall times, reducing switching losses by 22% vs. comparable SO-8 MOSFETs. |
Use Scenario: Point-of-load regulator on server motherboard supplying GPU core voltage. IC Role / Device Role / Timing Role: Synchronous rectifier (low-side FET) in dual-phase buck stage, driven by dedicated gate driver. Use Value: Triple-source pins and 1.95 K/W Rth(j-mb) maintain Tj < 110 °C at 70 A peak, eliminating need for external heatsink in 12 mm² footprint. |
| Industrial Load Switch | Hot-Swap Controller Back-End FET |
|
Use Scenario: 24 V motor control board requiring soft-start and overcurrent protection. IC Role / Device Role / Timing Role: Low-side load switch controlled via microcontroller GPIO with current sensing. Use Value: 1.81 V VGS(th) ensures full enhancement at 3.3 V logic; 63 A IS rating supports bidirectional current during braking regeneration. |
Use Scenario: 48 V datacom line card with hot-swap insertion into live backplane. IC Role / Device Role / Timing Role: Main pass FET in hot-swap controller IC reference design, handling inrush limiting and fault isolation. Use Value: 390 A pulsed IDM and 34.5 mJ avalanche energy withstand repeated 10 µs short-circuit events without failure during hot-plug sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRLHS6342TRPBF | 20 V VDS, 3.8 mΩ RDS(on) @ 4.5 V, PowerPAIR 3.3×3.3 package, higher Ciss (1720 pF) | Limited to ≤20 V systems; less avalanche ruggedness (no published EAS) | Select when 20 V rating suffices and lower RDS(on) at 4.5 V is prioritized over 25 V margin and avalanche capability. |
| DMTH3007LPSQ-13 | 30 V VDS, 5.2 mΩ RDS(on) @ 4.5 V, PowerDI5060 package, higher QG (13.5 nC) | Broadens voltage headroom but increases switching loss and gate drive demand | Select when 30 V rating is mandatory for transient tolerance and thermal derating is acceptable for same current density. |
Compared with IRLHS6342TRPBF and DMTH3007LPSQ-13, PSMN3R9-25MLC uniquely balances 25 V rating, sub-5 mΩ on-resistance at 4.5 V, ultra-low QGD, and verified avalanche energy-making it optimal for industrial 24 V DC-DC and load-switch designs demanding both efficiency and ruggedness.
Availability
PSMN3R9-25MLC is available at Aetrix Electronics and suitable for DC-DC converters, synchronous buck regulators, and industrial load switching requiring stable component supply, long-term lifecycle support, and traceable sourcing for production ramp.
Supply support for PSMN3R9-25MLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified and industrial-grade MOSFETs, ESD protection, and logic ICs.
PSMN3R9-25MLC belongs to Nexperia's NextPower Superjunction MOSFET product line, engineered specifically for high-efficiency, high-density power conversion in industrial, communications, and computing equipment where thermal performance and gate-drive simplicity are critical.
FAQ
What is the maximum continuous drain current for PSMN3R9-25MLC at 100 °C mounting base temperature?
At Tmb = 100 °C and VGS = 10 V, the maximum continuous drain current is 69 A per the Limiting Values table. This reflects thermal derating due to reduced heat dissipation capacity at elevated temperatures, not silicon current limit.
Does PSMN3R9-25MLC have an integrated body diode, and what is its reverse recovery performance?
Yes, it features a monolithic source-drain body diode with VSD = 0.82 V at IS = 25 A and Tj = 25 °C. Reverse recovery time trr is 17.6 ns with Qr = 9.2 nC, enabling efficient synchronous rectification in high-frequency buck converters without external Schottky diodes.
Can PSMN3R9-25MLC be used in avalanche mode, and what is its single-pulse energy rating?
Yes, it is specified for non-repetitive unclamped inductive switching. The single-pulse avalanche energy EAS is 34.5 mJ at Tj(init) = 25 °C, ID = 70 A, Vsup ≤ 25 V, and RGS = 50 Ω, as validated in Figure 3 of the datasheet.
What is the gate threshold voltage variation over temperature, and how does it affect system stability?
VGS(th) has a negative temperature coefficient of −4.1 mV/K. As junction temperature rises from 25 °C to 150 °C, VGS(th) decreases by ~515 mV, ensuring consistent turn-on behavior and preventing thermal runaway in parallel configurations or high-temperature environments.
PSMN3R9-25MLC,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SOT-1210, 8-LFPAK33 (5-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 25 V
- Current - Continuous Drain (Id) @ 25°C:
- 70A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 4.15mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 2.15V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 21.5 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1524 pF @ 12.5 V
- FET Feature:
- -
- Power Dissipation (Max):
- 69W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK33
PSMN3R9-25MLC,115 FAQ
1.How can I place an order for PSMN3R9-25MLC,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN3R9-25MLC,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN3R9-25MLC,115 reliable?
The price and inventory of PSMN3R9-25MLC,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN3R9-25MLC,115 is usually 5 days.
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5.How can I obtain technical support or documentation for PSMN3R9-25MLC,115?
For technical support, including PSMN3R9-25MLC,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN3R9-25MLC,115 requirements.
6.How does Aetrix verify that PSMN3R9-25MLC,115 is sourced from the original manufacturer or authorized distributors?
All PSMN3R9-25MLC,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN3R9-25MLC,115 meets industry standards.
7.What is the process for return or replacement of PSMN3R9-25MLC,115?
All PSMN3R9-25MLC,115 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN3R9-25MLC,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN3R9-25MLC,115 part is unused and in its original packaging.
Return procedure for PSMN3R9-25MLC,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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