Nexperia USA Inc. PSMN4R1-60YLX
- Part No.:
- PSMN4R1-60YLX
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SC-100, SOT-669
- Datasheet:
-
PSMN4R1-60YLX.pdf
- Description:
- MOSFET N-CH 60V 100A LFPAK56
- Quantity:
- Payment:

- Shipping:

Inventory:2,713
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PSMN4R1-60YL from Nexperia is a logic-level N-channel MOSFET in LFPAK56 (Power-SO8) package, rated for 60 V VDS, 4.1 mΩ RDS(on) at VGS = 10 V and 25 A, with 100 A continuous drain current capability at Tmb = 25 °C. It serves as a high-efficiency power switch in low-voltage synchronous rectification and fast-charge USB-PD circuits.
For engineers reviewing the PSMN4R1-60YL datasheet, PSMN4R1-60YL pinout, PSMN4R1-60YL application, or PSMN4R1-60YL equivalent, key selection criteria include its 3.3–4.8 mΩ RDS(on) at 5 V gate drive, avalanche-rated ruggedness (199 mJ), and thermal resistance of 0.63 K/W from junction to mounting base - critical for thermally constrained DC-DC and motor control designs.
Technical Context
This MOSFET employs Nexperia's TrenchMOS technology to achieve low on-resistance and low gate charge (QG(tot) = 54.8 nC, QGD = 18.1 nC at 5 V), enabling fast switching with reduced gate drive loss. Its logic-level threshold (VGS(th) = 1.4–2.1 V typ.) ensures full enhancement with standard 3.3 V or 5 V microcontroller outputs.
The device integrates an avalanche-rated body diode (VSD = 0.78–1.2 V at 25 A) and is qualified per industrial temperature limits (Tj = –55 to +175 °C). Mounting base (drain-connected) enables direct thermal coupling to heatsinks, supporting high-power density layouts in compact adapters and motor drivers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 60 V - Maximum blocking voltage for 48 V bus and LLC resonant converter primary-side applications. |
| RDS(on) | 3.3–4.8 mΩ @ VGS = 5 V, ID = 25 A, Tj = 25 °C - Enables <1 W conduction loss at 50 A, critical for high-current synchronous rectifiers. |
| ID (cont.) | 100 A @ Tmb = 25 °C - Package-limited current supports high-power USB-PD 100 W designs without parallel devices. |
| QGD | 18.1 nC @ VDS = 48 V, VGS = 5 V - Low gate-drain charge minimizes Miller-induced switching delay and improves hard-switching efficiency. |
| EAS | 199 mJ (non-repetitive) - Avalanche energy rating allows robust operation during inductive load turn-off transients in motor control. |
| Rth(j-mb) | 0.63 K/W - Enables >200 W power dissipation with modest heatsinking, supporting high-density board-level thermal management. |
| VGS(th) | 1.4–2.1 V @ ID = 1 mA - Ensures reliable turn-on with 3.3 V logic, eliminating need for gate boosters in battery-powered systems. |
Pinout & Package
LFPAK56 (SOT669) is a 4-lead plastic surface-mount package with exposed mounting base (drain-connected) for enhanced thermal performance. The package measures 5.8 × 3.8 mm with 1.27 mm lead pitch and supports reflow soldering per JEDEC J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three parallel source terminals reduce bond-wire inductance and improve current sharing in high-di/dt switching. |
| 4 | Gate (G) | Single gate input optimized for low-inductance PCB layout; requires <5 Ω external gate resistor for controlled dv/dt. |
| Mounting Base | Drain (D) | Exposed copper pad electrically connected to drain; must be soldered to large copper pour for thermal and electrical integrity. |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level gate drive | Turns fully on with 3.3 V or 5 V MCU GPIO, eliminating level-shifting circuitry in portable and adapter designs. |
| Avalanche ruggedness | 100% tested 199 mJ single-pulse energy rating ensures reliability in inductive switching without snubbers. |
| Low QG(tot)/QGD ratio | 54.8 nC total / 18.1 nC Miller charge → 3.03 ratio - improves switching speed and reduces ESW in high-frequency LLC converters. |
| Thermal performance | 0.63 K/W Rth(j-mb) enables >150 W continuous dissipation with 25 °C ambient and 20 cm² 2 oz copper heatsink. |
| LFPAK56 power density | Delivers 100 A current handling in 5.8 × 3.8 mm footprint - 2× higher current density than standard SO-8 MOSFETs. |
Applications
| USB-PD Fast Charging | Synchronous Rectification (LLC) |
|---|---|
|
Use Scenario: 100 W USB Power Delivery adapter with dual-phase output rectification. IC Role / Device Role / Timing Role: Primary-side synchronous rectifier switch replacing Schottky diodes in secondary-side LLC resonant converter. Use Value: Reduces conduction loss by >65% vs. 40 V Schottky, enabling >95% peak efficiency and eliminating forced-air cooling. |
Use Scenario: High-efficiency server PSU using asymmetric half-bridge LLC topology. IC Role / Device Role / Timing Role: Secondary-side synchronous rectifier operating at 200–500 kHz with zero-voltage switching (ZVS) timing. Use Value: 4.1 mΩ RDS(on) at 10 V gate drive sustains <0.5 W loss at 40 A, allowing compact transformer design and reduced output capacitance. |
| Battery-Powered Motor Control | LED TV Backlight Driver |
|
Use Scenario: 24 V cordless power tool controller with H-bridge BLDC driver stage. IC Role / Device Role / Timing Role: Low-side power switch in 3-phase inverter, driven by gate driver with 5 V logic interface. Use Value: Logic-level VGS(th) ensures full enhancement at battery voltages down to 18 V, maintaining torque at end-of-charge. |
Use Scenario: Local dimming backlight for 65″ 4K LCD TV with 128-zone LED string control. IC Role / Device Role / Timing Role: PWM-controlled current sink switch for constant-current LED strings operating at 12–24 V. Use Value: 100 A surge rating (IDM = 593 A) withstands inrush during hot-plug LED string activation without derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon IPP040N06N | RDS(on) = 4.0 mΩ @ 10 V, but VGS(th) = 2.2–3.3 V - less margin at 3.3 V drive. | Higher gate charge (QG = 62 nC) increases switching loss above 300 kHz. | Preferable where 10 V gate drive is available and thermal margin exceeds 10 K/W. |
| Vishay SI7850DP | RDS(on) = 3.9 mΩ @ 4.5 V, but no avalanche rating - requires external clamping in motor control. | SO-8 package (Rth(j-a) = 62 K/W) limits continuous current to 45 A at 25 °C ambient. | Only suitable for low-duty-cycle, non-inductive loads where avalanche stress is absent. |
Compared with IPP040N06N and SI7850DP, PSMN4R1-60YL delivers superior 3.3 V drive compatibility, industry-leading avalanche ruggedness, and 2.5× lower thermal resistance - making it optimal for space-constrained, high-reliability USB-PD and motor control applications.
Availability
PSMN4R1-60YL is available at Aetrix Electronics and suitable for USB-PD fast charging, synchronous rectification in LLC topologies, and battery-powered motor control requiring stable component supply across production lifecycles.
Supply support for PSMN4R1-60YL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic components, with leadership in automotive-qualified and industrial-grade MOSFETs.
This part belongs to Nexperia's LFPAK logic-level MOSFET product line, engineered specifically for high-efficiency, high-power-density power conversion in consumer, computing, and industrial equipment.
FAQ
What is the maximum continuous drain current at 100 °C mounting base temperature?
At Tmb = 100 °C, the continuous drain current remains 100 A - identical to the 25 °C rating - because current is package-limited, not thermally limited, per Figure 2 in the datasheet. Derating only applies above 100 °C due to thermal constraints.
Is the mounting base electrically isolated from the drain terminal?
No - the mounting base is internally connected to the drain (D), as confirmed in Table 2 (Pinning information) and Figure 17 (Package outline). This connection must be accounted for in PCB layout to avoid short circuits when the base is soldered to a grounded copper pour.
Does PSMN4R1-60YL support 3.3 V gate drive in production systems?
Yes - with VGS(th) ranging from 1.4 V (min) to 2.1 V (typ.) at 25 °C, the device achieves full enhancement at 3.3 V. Measured RDS(on) at VGS = 3.3 V is ≤7.2 mΩ (derated from Fig. 7), sufficient for most low-duty-cycle applications.
How does the avalanche rating impact design in motor control?
The 199 mJ non-repetitive avalanche energy (EAS) allows safe turn-off under inductive load conditions without external snubbers. In brushed DC motor H-bridges, this rating covers worst-case flyback energy from 100 A currents interrupted in <1 µs, reducing BOM count and layout complexity.
PSMN4R1-60YLX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- TrenchMOS™
- Package/Case:
- SC-100, SOT-669
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 60 V
- Current - Continuous Drain (Id) @ 25°C:
- 100A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 5V, 10V
- Rds On (Max) @ Id, Vgs:
- 4.1mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 2.1V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 103 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 7853 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 238W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56, Power-SO8
PSMN4R1-60YLX FAQ
1.How can I place an order for PSMN4R1-60YLX through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN4R1-60YLX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN4R1-60YLX reliable?
The price and inventory of PSMN4R1-60YLX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN4R1-60YLX is usually 5 days.
3.What payment methods are accepted for PSMN4R1-60YLX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN4R1-60YLX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN4R1-60YLX?
PSMN4R1-60YLX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN4R1-60YLX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN4R1-60YLX?
For technical support, including PSMN4R1-60YLX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN4R1-60YLX requirements.
6.How does Aetrix verify that PSMN4R1-60YLX is sourced from the original manufacturer or authorized distributors?
All PSMN4R1-60YLX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN4R1-60YLX meets industry standards.
7.What is the process for return or replacement of PSMN4R1-60YLX?
All PSMN4R1-60YLX units undergo pre-shipment inspection (PSI). If there is an issue with PSMN4R1-60YLX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN4R1-60YLX part is unused and in its original packaging.
Return procedure for PSMN4R1-60YLX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PSMN4R1-60YLX Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
