Nexperia USA Inc. PSMN4R2-30MLD/2X
- Part No.:
- PSMN4R2-30MLD/2X
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SOT-1210, 8-LFPAK33 (5-Lead)
- Datasheet:
-
PSMN4R2-30MLD/2X.pdf
- Description:
- PSMN4R2-30MLD/SOT1210/MLFPAK
- Quantity:
- Payment:

- Shipping:

Inventory:4,622
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Product details
Overview
PSMN4R2-30MLD from Nexperia is an N-channel 30 V, 4.2 mΩ logic-level MOSFET in LFPAK33 (SOT1210) package, optimized for 4.5 V gate drive and high-frequency synchronous rectification. It delivers ultra-low QG (9.2–13.8 nC), low RDS(on) (3.45 mΩ typ @ 10 V), and Schottky-like soft-recovery (s-factor > 1.05) with < 1 µA leakage at 25 °C. Used in secondary-side DC-DC conversion for telecom servers.
For engineers reviewing the PSMN4R2-30MLD datasheet, PSMN4R2-30MLD pinout, PSMN4R2-30MLD application, or PSMN4R2-30MLD equivalent, this page provides verified electrical specs, thermal performance (Rth(j-mb) = 2.09 K/W), LFPAK33 mounting base layout guidance, and validated alternatives for high-efficiency POL and VRM designs.
Technical Context
This MOSFET employs Nexperia's NextPowerS3 technology with "SchottkyPlus" body diode architecture, enabling soft reverse recovery (trr = 26–52 ns, Qr = 15–30 nC) without elevated leakage. Its gate threshold voltage (VGS(th) = 1.2–2.2 V) and low Ciss (1197–1795 pF) support stable 4.5 V logic-level switching up to 1 MHz.
The LFPAK33 package uses clip-bonded die attach and exposed drain mounting base (mb), delivering low parasitic inductance/resistance and 175 °C junction rating. Thermal resistance from junction to mounting base is 2.09 K/W, enabling high-current operation (70 A continuous @ Tmb = 25 °C) with minimal heatsinking.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V maximum - supports 24 V input rail systems with margin for transients |
| RDS(on) | 3.45 mΩ typical @ VGS = 10 V - enables < 0.1 W conduction loss at 50 A |
| QG(tot) | 9.2–13.8 nC @ VGS = 4.5 V - minimizes gate drive power and switching loss at 500 kHz+ |
| trr / Qr | 26–52 ns / 15–30 nC - reduces EMI and voltage overshoot during hard commutation |
| Rth(j-mb) | 2.09 K/W - allows direct thermal coupling to PCB copper or heatsink via exposed drain pad |
| ID (cont) | 70 A @ Tmb = 25 °C - rated for high-current POL modules with forced-air or board-level cooling |
| VGS(th) | 1.2–2.2 V - ensures full enhancement with standard 3.3 V/5 V logic drivers |
Pinout & Package
LFPAK33 (SOT1210) is a leadless, clip-bonded surface-mount package with exposed drain mounting base (mb) for low-inductance, high-power thermal transfer. It features no wire bonds or adhesive, qualified to 175 °C junction temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three parallel source terminals reduce source inductance and improve current sharing in high-di/dt applications |
| 4 | Gate (G) | Single gate terminal with low RG (0.48–0.95 Ω) for fast, controlled turn-on/turn-off |
| mb | Mounting Base / Drain (D) | Exposed copper drain pad - serves as primary thermal path and high-current drain connection; soldered directly to PCB thermal plane |
Key Features
| Feature | Design Value |
|---|---|
| "SchottkyPlus" body diode | Soft reverse recovery (s-factor > 1.05) with < 1 µA leakage at 25 °C - eliminates need for external Schottky while avoiding leakage trade-offs |
| Ultra-low QG/QGD | 9.2–13.8 nC total gate charge and 3.1–4.6 nC gate-drain charge - enables high-efficiency operation above 1 MHz switching frequency |
| Optimized for 4.5 V drive | RDS(on) = 4.5–5.7 mΩ @ VGS = 4.5 V - ensures full enhancement using standard logic-level drivers without level-shifting |
| Clip-bonded LFPAK33 | No wire bonds or die attach glue - improves power cycling reliability and thermal stability up to 175 °C junction temperature |
| Exposed drain mounting base | Direct thermal interface to PCB - achieves 2.09 K/W junction-to-mounting-base resistance for compact high-power layouts |
Applications
| Server DC-DC Conversion | Telecom Secondary-Side SR |
|---|---|
|
Use Scenario: High-density 12 V → 1 V/3.3 V point-of-load converters in rack-mounted servers. IC Role / Device Role / Timing Role: Synchronous rectifier on secondary side of isolated forward or LLC converter, operating at 300–800 kHz. Use Value: Low RDS(on) and soft-recovery minimize conduction + switching losses, improving efficiency by ≥0.8% vs. standard MOSFETs at 50 A load. |
Use Scenario: Secondary-side synchronous rectification in 48 V telecom PSUs powering base station RF modules. IC Role / Device Role / Timing Role: Low-voltage, high-current rectifier replacing Schottky diodes in phase-shifted full-bridge topologies. Use Value: SchottkyPlus diode behavior reduces voltage overshoot and EMI, allowing smaller output filters and meeting CISPR-32 Class B limits without shielding. |
| VRM for GPU/ASIC | Brushless Motor Control |
|
Use Scenario: Voltage regulator module supplying dynamic core voltage (Vcore) to AI accelerators and high-end GPUs. IC Role / Device Role / Timing Role: High-side or low-side switch in multiphase buck converters with 500 kHz–1 MHz PWM frequency. Use Value: Ultra-low QG and optimized gate charge profile enable precise dead-time control and reduced shoot-through risk under rapid load transients. |
Use Scenario: Inverter leg switch in 24 V BLDC motor drives for industrial automation and HVAC fans. IC Role / Device Role / Timing Role: Low-side switching element in 3-phase bridge, commutating up to 40 A peak current at 20 kHz PWM. Use Value: Robust avalanche rating (59 mJ) and 175 °C rating ensure reliable operation during regenerative braking and short-circuit events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon IPP040N04L | RDS(on) = 4.0 mΩ @ 10 V; QG = 14.5 nC @ 4.5 V; TO-252 package | Higher package inductance and Rth(j-a) = 57 K/W - requires larger PCB copper area for thermal management | Prefer when TO-252 footprint compatibility is required and switching frequency ≤ 300 kHz. |
| Vishay SiR626DP | RDS(on) = 3.8 mΩ @ 10 V; QG = 12.5 nC @ 4.5 V; PowerPAK SO-8L package | No exposed drain pad - Rth(j-mb) not specified; relies on leads for thermal transfer | Choose when legacy SO-8L layout reuse is critical and thermal budget allows higher junction rise. |
Compared with IPP040N04L and SiR626DP, PSMN4R2-30MLD offers superior thermal performance via its exposed drain mounting base (2.09 K/W), lower leakage (<1 µA), and softer diode recovery - making it optimal for high-frequency, high-reliability POL and telecom SR where EMI and thermal density are constrained.
Availability
PSMN4R2-30MLD is available at Aetrix Electronics and suitable for server DC-DC conversion, telecom secondary-side synchronous rectification, and GPU/ASIC VRMs requiring stable component supply, long-lifecycle assurance, and traceable sourcing.
Supply support for PSMN4R2-30MLD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified and industrial-grade MOSFETs, ESD protection, and logic ICs.
This device belongs to the NextPowerS3 portfolio, engineered specifically for high-efficiency, high-frequency power conversion in data center, telecom, and computing infrastructure - emphasizing low-loss switching, robust thermal design, and Schottky-like diode performance without leakage penalties.
FAQ
What is the maximum continuous drain current for PSMN4R2-30MLD at 100 °C mounting base temperature?
The datasheet specifies 65 A continuous drain current at Tmb = 100 °C and VGS = 10 V (Table 5, Limiting Values). This derating reflects thermal limits of the LFPAK33 package and is confirmed in Figure 2 - not a silicon limitation but a safe operating area constraint based on package power dissipation capability.
Does PSMN4R2-30MLD have avalanche energy rating, and how is it tested?
Yes - it has a non-repetitive drain-source avalanche energy rating of 59 mJ (Table 5), measured under unclamped inductive switching conditions: VGS = 10 V, Tj(init) = 25 °C, ID = 25 A, Vsup ≤ 30 V, RGS = 50 Ω, tp = 122 µs. This rating is 100% production-tested per datasheet footnote [2].
Can PSMN4R2-30MLD be driven directly by a 3.3 V microcontroller GPIO?
Yes - its gate threshold voltage range is 1.2–2.2 V (Table 7), and RDS(on) remains low (≤5.7 mΩ) at VGS = 4.5 V. At 3.3 V, it operates in enhanced mode but with higher RDS(on); for full performance, use a dedicated 4.5–5 V gate driver. The device is explicitly optimized for 4.5 V drive, not 3.3 V saturation.
How does the "SchottkyPlus" body diode differ from a standard MOSFET body diode in practice?
SchottkyPlus delivers soft reverse recovery (s-factor > 1.05) and low Qr (15–30 nC), mimicking Schottky diode behavior during turn-off - reducing voltage spikes and EMI. Crucially, it maintains <1 µA leakage at 25 °C, unlike integrated Schottky MOSFETs which typically exhibit >10 µA leakage, enabling use in standby-sensitive applications.
PSMN4R2-30MLD/2X Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SOT-1210, 8-LFPAK33 (5-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 70A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 4.3mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 2.2V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 29.3 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1795 pF @ 15 V
- FET Feature:
- Schottky Diode (Body)
- Power Dissipation (Max):
- 65W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK33
PSMN4R2-30MLD/2X FAQ
1.How can I place an order for PSMN4R2-30MLD/2X through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN4R2-30MLD/2X on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN4R2-30MLD/2X reliable?
The price and inventory of PSMN4R2-30MLD/2X are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN4R2-30MLD/2X is usually 5 days.
3.What payment methods are accepted for PSMN4R2-30MLD/2X?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN4R2-30MLD/2X transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN4R2-30MLD/2X?
PSMN4R2-30MLD/2X orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN4R2-30MLD/2X order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN4R2-30MLD/2X?
For technical support, including PSMN4R2-30MLD/2X datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN4R2-30MLD/2X requirements.
6.How does Aetrix verify that PSMN4R2-30MLD/2X is sourced from the original manufacturer or authorized distributors?
All PSMN4R2-30MLD/2X products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN4R2-30MLD/2X meets industry standards.
7.What is the process for return or replacement of PSMN4R2-30MLD/2X?
All PSMN4R2-30MLD/2X units undergo pre-shipment inspection (PSI). If there is an issue with PSMN4R2-30MLD/2X, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN4R2-30MLD/2X part is unused and in its original packaging.
Return procedure for PSMN4R2-30MLD/2X:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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