Nexperia USA Inc. PSMN6R0-30YLD/2X
- Part No.:
- PSMN6R0-30YLD/2X
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SC-100, SOT-669
- Datasheet:
-
PSMN6R0-30YLD/2X.pdf
- Description:
- PSMN6R0-30YLD/SOT669/LFPAK
- Quantity:
- Payment:

- Shipping:

Inventory:4,493
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Product details
Overview
PSMN6R0-30YLD from Nexperia is an N-channel 30 V, 6.0 mΩ logic-level MOSFET in LFPAK56 (SOT669) package, optimized for 4.5 V gate drive and high-frequency synchronous rectification. It delivers 66 A continuous drain current at Tmb = 25 °C, features ultra-low QG (6.5 nC @ 4.5 V), and uses NextPowerS3 SchottkyPlus technology to achieve soft-recovery (s-factor > 1) with < 1 µA leakage at 25 °C - enabling high-efficiency DC/DC conversion in telecom VRMs.
For engineers reviewing the PSMN6R0-30YLD datasheet, PSMN6R0-30YLD pinout, PSMN6R0-30YLD application, or PSMN6R0-30YLD equivalent, key selection criteria include RDS(on) at 4.5 V (6.7–8.35 mΩ), junction-to-mounting-base thermal resistance (3 K/W), avalanche energy rating (46 mJ), and LFPAK56's clip-bonded, wire-bond-free construction qualified to 175 °C.
Technical Context
This MOSFET employs Nexperia's NextPowerS3 architecture with SchottkyPlus body diode integration, delivering low reverse recovery charge (Qr = 12.6 nC) and fast trr (23.4 ns) without elevated leakage. Its gate threshold voltage (VGS(th) = 1.2–2.2 V) and low Ciss (832 pF) support stable 4.5 V logic-level switching in high-density POL converters.
The device uses a copper-clip bonded die attach in LFPAK56, eliminating wire bonds and adhesive. This yields low parasitic inductance and resistance, enabling clean turn-on/turn-off waveforms (td(on) = 9 ns, tf = 10.9 ns) and reduced EMI in >500 kHz switching applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V maximum - supports 24 V input rail systems with margin for transients |
| RDS(on) @ 4.5 V | 6.7–8.35 mΩ typical - enables high efficiency at logic-level gate drive in VRMs |
| QG(tot) | 6.5 nC @ 4.5 V - reduces gate drive power loss in high-frequency (>1 MHz) operation |
| Qr | 12.6 nC - minimizes body diode conduction loss during synchronous rectification |
| Rth(j-mb) | 3 K/W - allows 47 W power dissipation with minimal thermal derating on standard PCBs |
| Softness factor (S) | >1 - ensures controlled, non-oscillatory reverse recovery for low EMI layout |
| VGS(th) | 1.2–2.2 V - guarantees reliable enhancement-mode turn-on with 3.3 V or 5 V logic |
Pinout & Package
LFPAK56 (SOT669) is a surface-mount, clip-bonded Power-SO8 package with exposed mounting base connected to drain. It eliminates wire bonds and adhesive, achieving 175 °C qualification and wave-solder compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source (S) | Three parallel source terminals reduce source inductance and improve current sharing in high-di/dt paths |
| 4 | Gate (G) | Single low-inductance gate connection optimized for fast, ringing-free switching |
| Mounting base (mb) | Drain (D) | Exposed copper pad electrically and thermally connected to drain - serves as primary heat path and high-current return |
Key Features
| Feature | Design Value |
|---|---|
| SchottkyPlus body diode | Enables synchronous rectification with Qr = 12.6 nC and trr = 23.4 ns while maintaining <1 µA leakage at 25 °C |
| Ultra-low QGD | 1.8 nC @ 4.5 V - suppresses Miller-induced shoot-through in half-bridge configurations |
| Clip-bonded construction | Eliminates wire bonds and die attach glue - improves reliability and thermal cycling endurance up to 175 °C junction |
| Optimized for 4.5 V drive | RDS(on) remains ≤8.35 mΩ at Tj = 25 °C - ensures full enhancement with standard logic-level controllers |
| Low parasitic inductance | Minimizes voltage spikes during turn-off (dV/dt > 10 V/ns) - reduces need for snubbers in compact layouts |
Applications
| Server DC/DC Conversion | Telecom Secondary-Side SR |
|---|---|
|
Use Scenario: On-board 12 V to 1.2 V/50 A point-of-load conversion in rack-mounted servers. IC Role / Device Role / Timing Role: Primary synchronous rectifier switch in multiphase buck converter operating at 600 kHz. Use Value: 6.7 mΩ RDS(on) at 4.5 V reduces conduction loss by 32% vs. legacy 10 mΩ MOSFETs, improving system efficiency by 1.8% at full load. |
Use Scenario: Secondary-side synchronous rectification in 48 V input telecom PSUs delivering 12 V/60 A output. IC Role / Device Role / Timing Role: Low-side switch replacing Schottky diodes in forward or LLC secondary stage. Use Value: Soft-recovery (s-factor > 1) and 23.4 ns trr eliminate voltage overshoot across transformer windings, reducing EMI filter size by 40%. |
| GPU Voltage Regulator | Brushless Motor Drive |
|
Use Scenario: High-current V-core regulation for discrete GPUs requiring dynamic 0.8–1.3 V output at up to 120 A peak. IC Role / Device Role / Timing Role: High-side switch in 3-phase interleaved buck converter with 1 MHz switching frequency. Use Value: 6.5 nC QG(tot) at 4.5 V cuts gate drive loss by 55% versus comparable 12 nC devices, lowering driver IC thermal load. |
Use Scenario: Low-side phase switch in 24 V, 3-phase BLDC motor controller for industrial fans and pumps. IC Role / Device Role / Timing Role: Fast-switching, low-RDS(on) power stage element handling 30 A RMS current with PWM at 20 kHz. Use Value: Junction-to-mounting-base Rth = 3 K/W enables direct heatsink mounting without thermal interface material, simplifying mechanical design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSMN5R5-30YLH | Lower RDS(on) (5.5 mΩ @ 4.5 V) but higher QG (8.1 nC); same LFPAK56 package | Better conduction loss at high DC load, but increased gate drive loss above 300 kHz | Select when static efficiency dominates; avoid in >500 kHz designs due to higher switching loss |
| IRLHS6342 | Higher RDS(on) (7.5 mΩ @ 4.5 V), lower Qr (9.2 nC), PQFN 3.3×3.3 mm package | Smaller footprint but higher conduction loss and no SchottkyPlus soft recovery | Prefer for space-constrained designs where EMI is less critical and thermal budget permits higher RDS(on) |
Compared with PSMN5R5-30YLH and IRLHS6342, PSMN6R0-30YLD uniquely balances ultra-low QG, soft-recovery, and 6.0 mΩ RDS(on) in a thermally robust LFPAK56 - making it optimal for high-frequency, high-reliability telecom and server POL applications where both efficiency and EMI must be simultaneously minimized.
Availability
PSMN6R0-30YLD is available at Aetrix Electronics and suitable for server DC/DC conversion, telecom secondary-side synchronous rectification, and GPU voltage regulator modules requiring stable component supply and long-term industrial lifecycle support.
Supply support for PSMN6R0-30YLD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors - delivering discrete, logic, and MOSFET solutions for automotive, industrial, and computing markets.
PSMN6R0-30YLD belongs to the NextPowerS3 portfolio, engineered specifically for high-efficiency, high-frequency power conversion in datacenter and telecom infrastructure where low QG, soft-recovery, and thermal robustness are mandatory.
FAQ
What is the maximum continuous drain current for PSMN6R0-30YLD at 100 °C mounting base temperature?
The datasheet specifies 46 A continuous drain current (ID) at Tmb = 100 °C and VGS = 10 V. This reflects thermal derating from the 66 A rating at 25 °C, based on the device's 3 K/W junction-to-mounting-base thermal resistance and SOA limits under steady-state conditions.
Does PSMN6R0-30YLD support gate drive voltages below 4.5 V?
Yes - its gate threshold voltage (VGS(th)) ranges from 1.2 V to 2.2 V, enabling turn-on with 3.3 V logic. However, RDS(on) increases significantly below 4.5 V: at VGS = 3.5 V and ID = 15 A, RDS(on) rises to ~10.5 mΩ (typical), so 4.5 V is the minimum recommended for efficient operation.
How is the mounting base (drain) electrically isolated during PCB layout?
The mounting base is internally connected to the drain terminal and must be routed as part of the high-current drain path. It is not electrically isolated - isolation is achieved by maintaining clearance/creepage to adjacent traces and using appropriate solder mask-defined thermal pads. No insulation layer is required or recommended beneath the base.
Is PSMN6R0-30YLD qualified for automotive applications?
No - this device is not AEC-Q101 qualified and is explicitly designated for industrial and computing applications. Nexperia's datasheet states it is "non-automotive qualified" and unsuitable for safety-critical or life-support systems without additional customer validation and risk assumption.
PSMN6R0-30YLD/2X Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SC-100, SOT-669
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 66A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 6mOhm @ 15A, 10V
- Vgs(th) (Max) @ Id:
- 2.2V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 13.7 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 832 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 47W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56, Power-SO8
PSMN6R0-30YLD/2X FAQ
1.How can I place an order for PSMN6R0-30YLD/2X through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN6R0-30YLD/2X on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN6R0-30YLD/2X reliable?
The price and inventory of PSMN6R0-30YLD/2X are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN6R0-30YLD/2X is usually 5 days.
3.What payment methods are accepted for PSMN6R0-30YLD/2X?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN6R0-30YLD/2X transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN6R0-30YLD/2X?
PSMN6R0-30YLD/2X orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN6R0-30YLD/2X order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN6R0-30YLD/2X?
For technical support, including PSMN6R0-30YLD/2X datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN6R0-30YLD/2X requirements.
6.How does Aetrix verify that PSMN6R0-30YLD/2X is sourced from the original manufacturer or authorized distributors?
All PSMN6R0-30YLD/2X products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN6R0-30YLD/2X meets industry standards.
7.What is the process for return or replacement of PSMN6R0-30YLD/2X?
All PSMN6R0-30YLD/2X units undergo pre-shipment inspection (PSI). If there is an issue with PSMN6R0-30YLD/2X, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN6R0-30YLD/2X part is unused and in its original packaging.
Return procedure for PSMN6R0-30YLD/2X:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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