Nexperia USA Inc. PSMN6R1-30YLDX
- Part No.:
- PSMN6R1-30YLDX
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SC-100, SOT-669
- Datasheet:
-
PSMN6R1-30YLDX.pdf
- Description:
- MOSFET N-CH 30V 66A LFPAK56
- Quantity:
- Payment:

- Shipping:

Inventory:2,088
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Product details
Overview
PSMN6R1-30YLD from Nexperia is an N-channel 30 V logic-level MOSFET in LFPAK56 (SOT669) package, optimized for 4.5 V gate drive with RDS(on) = 6.5 mΩ @ VGS = 4.5 V, 15 A, Tj = 25 °C. It delivers ultra-low gate charge (QG(tot) = 6.8–10.2 nC), soft-recovery diode (s-factor > 1), and <1 µA leakage at 25 °C - enabling high-efficiency synchronous rectification in telecom POL modules.
For engineers reviewing the PSMN6R1-30YLD datasheet, PSMN6R1-30YLD pinout, PSMN6R1-30YLD application, or PSMN6R1-30YLD equivalent, this page provides verified electrical specs, thermal performance (Rth(j-mb) = 3 K/W), LFPAK56 mounting base configuration, and validated alternatives for server DC-DC and VRM designs.
Technical Context
This MOSFET uses Nexperia's NextPowerS3 technology with "SchottkyPlus" body diode architecture, achieving Schottky-like low reverse recovery charge (Qr = 12.6–25.2 nC) and softness factor ≥1.3 while maintaining leakage <1 µA at 25 °C - eliminating trade-offs between EMI and diode leakage common in integrated-Schottky devices.
Its LFPAK56 Power-SO8 package features clip-bonded die attach and exposed mounting base connected to drain, delivering low parasitic inductance/resistance and 175 °C junction rating. Gate threshold voltage is 1.2–2.2 V, enabling robust turn-on at 4.5 V with minimal Miller plateau (VGS(pl) = 2.7 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V maximum - supports 24 V input rail systems with margin for transients in telecom/server power supplies. |
| RDS(on) | 6.5 mΩ @ 4.5 V, 15 A, 25 °C - enables <1 W conduction loss at 40 A in parallel configurations for high-current POL stages. |
| QG(tot) | 6.8–10.2 nC @ 4.5 V - reduces gate drive power and switching losses in 500 kHz–1 MHz VRM applications. |
| QGD | 2.1–3.15 nC @ 4.5 V - minimizes Miller-induced shoot-through risk during hard-switching in synchronous buck converters. |
| Rth(j-mb) | 3 K/W - allows 47 W total dissipation at 25 °C mounting base temperature, supporting high-power density without heatsinks. |
| s-factor | >1 - ensures soft reverse recovery, reducing voltage spikes and EMI in secondary-side rectification circuits. |
| ID | 66 A continuous @ Tmb = 25 °C - supports high peak current demands in GPU/V-core power delivery with derating. |
Pinout & Package
LFPAK56 (SOT669) is a clip-bonded, wave-solderable surface-mount package with exposed mounting base (drain-connected) and no wire bonds or die attach glue. It achieves 175 °C qualification and low-inductance layout via direct copper-to-die thermal path.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source | Three parallel source terminals reduce source inductance and improve current sharing in high-di/dt switching. |
| 4 | Gate | Single gate input with low RG (0.44–0.88 Ω) - compatible with standard gate drivers without external series resistance. |
| Mounting Base (mb) | Drain | Exposed copper pad electrically and thermally connected to drain - serves as primary heat path and high-current return node. |
Key Features
| Feature | Design Value |
|---|---|
| "SchottkyPlus" body diode | Qr = 12.6–25.2 nC and s-factor ≥1.3 with leakage <1 µA @ 25 °C - eliminates need for external Schottky in cost-sensitive POL designs. |
| Ultra-low QG, QGD, QOSS | QG(tot) = 6.8–10.2 nC, QGD = 2.1–3.15 nC, QOSS = 11.8 nC - enables >1 MHz operation with <5% gate drive loss in 12 V input VRMs. |
| Optimized for 4.5 V drive | VGS(th) = 1.2–2.2 V and RDS(on) = 6.5 mΩ @ 4.5 V - ensures full enhancement with standard logic-level controllers like TI UCC28950 or ON Semi NCP4306. |
| High-reliability construction | Clip-bonded die, solder die attach, no wire bonds or epoxy - qualified to 175 °C junction and 260 °C peak soldering temperature per JEDEC J-STD-020. |
Applications
| Server On-Board DC-DC | Telecom Secondary-Side SR |
|---|---|
|
Use Scenario: Point-of-load conversion from 12 V intermediate bus to 1.8 V/60 A for ASICs in cloud servers. IC Role / Device Role / Timing Role: Synchronous rectifier switch in multiphase buck converter, operating at 600 kHz with 4.5 V gate drive. Use Value: 6.5 mΩ RDS(on) and 3 K/W thermal resistance enable >95% efficiency at full load without forced air cooling. |
Use Scenario: Secondary-side synchronous rectification in 48 V–12 V isolated DC-DC for 5G base station power supplies. IC Role / Device Role / Timing Role: Low-voltage-side switch replacing Schottky diodes in active clamp forward topology. Use Value: Soft-recovery (s-factor >1) and low Qr reduce output voltage overshoot and EMI filter size by 30% vs. standard MOSFETs. |
| GPU/V-Core VRM | Brushless Motor Control |
|
Use Scenario: High-current power stage for discrete GPU core voltage regulation (0.8–1.2 V, up to 300 A). IC Role / Device Role / Timing Role: High-side and low-side switch in dual-phase interleaved buck with 1 MHz switching frequency. Use Value: Ultra-low QGD (2.1–3.15 nC) suppresses Miller-induced false turn-on, enabling reliable operation with 5 V gate drivers. |
Use Scenario: Inverter leg in 24 V BLDC motor driver for industrial automation actuators. IC Role / Device Role / Timing Role: Low-side switching element in 3-phase bridge, driven by gate driver with 4.5 V output. Use Value: 66 A continuous current rating and 263 A pulsed capability support 5× overload peaks without thermal shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon BSC014N04LS6 | RDS(on) = 1.4 mΩ @ 4.5 V but 40 V VDS; QG(tot) = 12.5 nC - higher conduction loss margin but larger gate drive demand. | Higher voltage rating suits 36 V industrial rails; less optimal for 24 V telecom due to over-spec'd VDS. | Choose when 40 V rating and lower RDS(on) outweigh gate charge penalty in lower-frequency (<500 kHz) designs. |
| Vishay SiR626DP | RDS(on) = 5.8 mΩ @ 4.5 V, same 30 V rating; QG(tot) = 10.5 nC; no specified s-factor or SchottkyPlus diode. | Lacks soft-recovery diode - requires external snubbers in high-di/dt synchronous rectification. | Prefer where lowest RDS(on) is critical and diode performance is managed externally or not required. |
Compared with PSMN6R1-30YLD, BSC014N04LS6 trades higher gate charge for lower on-resistance and wider voltage margin, while SiR626DP offers marginally lower RDS(on) but lacks verified soft-recovery - making PSMN6R1-30YLD optimal for EMI-sensitive, high-frequency telecom POL where diode behavior is integral.
Availability
PSMN6R1-30YLD is available at Aetrix Electronics and suitable for server on-board DC-DC, telecom secondary-side synchronous rectification, and GPU/V-core VRM applications requiring stable component supply across multi-year production cycles.
Supply support for PSMN6R1-30YLD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified and industrial-grade MOSFETs.
This device belongs to the NextPowerS3 portfolio, engineered specifically for high-efficiency, high-frequency power conversion in data center, telecom, and computing infrastructure where low EMI and thermal robustness are mandatory.
FAQ
What is the maximum continuous drain current at 100 °C mounting base temperature?
The PSMN6R1-30YLD supports 46 A continuous drain current at Tmb = 100 °C, as specified in Table 5 (Limiting Values). This derating reflects thermal constraints of the LFPAK56 package and ensures safe operation within its 175 °C junction limit under sustained load conditions.
Does this MOSFET require a gate resistor for stability in 1 MHz switching applications?
No external gate resistor is required for stability: the device has intrinsic gate resistance of 0.44–0.88 Ω and ultra-low QGD (2.1–3.15 nC), enabling clean turn-on/turn-off with standard 5 V gate drivers. However, a 2–5 Ω series resistor is recommended to dampen ringing in layouts with long gate traces.
Is the mounting base electrically isolated from other terminals?
No - the mounting base is internally connected to the drain terminal, as confirmed in Pinning Information (Table 2) and Package Outline (Fig. 17). It must be routed to the high-side DC node or heatsink with appropriate insulation if thermal sinking to chassis ground is required.
How does the "SchottkyPlus" diode compare to a discrete Schottky in reverse recovery performance?
The "SchottkyPlus" diode achieves Qr = 12.6–25.2 nC and trr = 23.8–47.6 ns - matching discrete Schottky performance - while maintaining leakage <1 µA at 25 °C, unlike conventional Schottky diodes which typically exceed 100 µA at same voltage and temperature.
PSMN6R1-30YLDX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SC-100, SOT-669
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 66A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 6mOhm @ 15A, 10V
- Vgs(th) (Max) @ Id:
- 2.2V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 13.6 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 817 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 47W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK56, Power-SO8
PSMN6R1-30YLDX FAQ
1.How can I place an order for PSMN6R1-30YLDX through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN6R1-30YLDX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN6R1-30YLDX reliable?
The price and inventory of PSMN6R1-30YLDX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN6R1-30YLDX is usually 5 days.
3.What payment methods are accepted for PSMN6R1-30YLDX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMN6R1-30YLDX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMN6R1-30YLDX?
PSMN6R1-30YLDX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMN6R1-30YLDX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMN6R1-30YLDX?
For technical support, including PSMN6R1-30YLDX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN6R1-30YLDX requirements.
6.How does Aetrix verify that PSMN6R1-30YLDX is sourced from the original manufacturer or authorized distributors?
All PSMN6R1-30YLDX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN6R1-30YLDX meets industry standards.
7.What is the process for return or replacement of PSMN6R1-30YLDX?
All PSMN6R1-30YLDX units undergo pre-shipment inspection (PSI). If there is an issue with PSMN6R1-30YLDX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN6R1-30YLDX part is unused and in its original packaging.
Return procedure for PSMN6R1-30YLDX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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