Nexperia USA Inc. PSMN9R0-25MLC,115
- Part No.:
- PSMN9R0-25MLC,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- SOT-1210, 8-LFPAK33 (5-Lead)
- Datasheet:
-
PSMN9R0-25MLC,115.pdf
- Description:
- MOSFET N-CH 25V 55A LFPAK33
- Quantity:
- Payment:

- Shipping:

Inventory:1,397
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Product details
Overview
PSMN9R0-25MLC from Nexperia is a logic-level enhancement-mode N-channel MOSFET in LFPAK33 (SOT1210) package, rated for 25 V VDS, 8.65 mΩ RDS(on) at VGS = 10 V and 15 A, optimized for 4.5 V gate drive using NextPower Superjunction technology, and deployed in synchronous buck regulators and DC-to-DC converters.
For engineers reviewing the PSMN9R0-25MLC datasheet, PSMN9R0-25MLC pinout, PSMN9R0-25MLC application, or PSMN9R0-25MLC equivalent, this device supports high-efficiency power conversion with ultra-low QG, QGD, and QOSS, low thermal resistance (3.1 K/W), and avalanche ruggedness (8.7 mJ), making it suitable for industrial and communications load switching where compact footprint and robust transient handling are critical.
Technical Context
This MOSFET employs NextPower Superjunction architecture to minimize conduction and switching losses simultaneously. Its gate threshold voltage (1.3–1.95 V) and low RDS(on) temperature coefficient enable stable operation across -55 °C to 175 °C junction range.
The LFPAK33 package integrates a thermally enhanced mounting base connected to drain, delivering 3.1 K/W junction-to-mounting-base thermal resistance and supporting 55 A continuous drain current at Tmb = 25 °C. Its 1.2 nC QGD and 5.4 nC QG(tot) at 4.5 V gate drive ensure fast, low-loss switching in high-frequency synchronous rectification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 25 V - Maximum drain-source blocking voltage; defines safe operating ceiling in 24 V rail applications. |
| RDS(on) @ VGS = 10 V | 7.55–8.65 mΩ - Confirmed on-resistance at full gate drive; enables <1 W conduction loss at 40 A. |
| RDS(on) @ VGS = 4.5 V | 9.8–11.3 mΩ - Verified logic-level performance; ensures reliable turn-on from standard microcontroller GPIOs. |
| QGD | 1.2 nC - Gate-drain charge directly governs Miller-induced switching delay and EMI; low value improves hard-switching efficiency. |
| QG(tot) @ 4.5 V | 5.4 nC - Total gate charge determines driver strength requirement; enables use with low-power gate drivers. |
| Rth(j-mb) | 3.1–3.32 K/W - Junction-to-mounting-base thermal resistance; allows direct heatsinking without PCB copper pour dependency. |
| EAS | 8.7 mJ - Non-repetitive avalanche energy rating; provides margin against inductive turn-off transients in buck converter freewheeling. |
Pinout & Package
LFPAK33 (SOT1210) is a surface-mount plastic package with exposed mounting base (drain-connected) and four leads: three source terminals and one gate terminal. The package offers low parasitic inductance and resistance, optimized for high-current, high-frequency power switching.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | Source | Three parallel source connections reduce current density and package inductance; support >40 A pulsed current paths. |
| 4 | Gate | Single gate input with 1.9 Ω typical gate resistance; compatible with standard 5 V/3.3 V logic-level drivers. |
| Mounting Base (mb) | Drain | Exposed metal pad electrically and thermally connected to drain; serves as primary heat path and high-current return node. |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level gate drive compatibility | Operates fully enhanced at VGS = 4.5 V, eliminating need for gate boosters in 5 V systems. |
| Ultra-low QG, QGD, QOSS | Reduces switching losses by >30% vs. conventional trench MOSFETs at 500 kHz, improving system efficiency in DC-DC stages. |
| NextPower Superjunction technology | Enables 25 V rating with sub-10 mΩ RDS(on) in LFPAK33, achieving higher power density than DPAK alternatives. |
| Low parasitic inductance/resistance | Minimizes voltage overshoot and ringing during hard switching, reducing snubber requirements in synchronous buck designs. |
| Avalanche ruggedness | Rated for 8.7 mJ single-pulse unclamped avalanche energy, enabling robust operation under inductive load faults. |
Applications
| DC-to-DC Converters | Load Switching |
|---|---|
|
Use Scenario: High-efficiency point-of-load (POL) converters in telecom baseband units and server VRMs. IC Role / Device Role / Timing Role: Synchronous rectifier in 25 V input, 3.3–12 V output buck topology operating at 300–1000 kHz. Use Value: 8.65 mΩ RDS(on) and 5.4 nC QG at 4.5 V enable >95% efficiency at 20 A load while maintaining thermal stability on compact PCBs. |
Use Scenario: Hot-swap and power sequencing control in industrial PLC I/O modules. IC Role / Device Role / Timing Role: Low-side load switch managing 24 V supply to field sensors and actuators with controlled inrush. Use Value: 1.5 V typical VGS(th) and 11.3 mΩ RDS(on) at 4.5 V ensure clean turn-on from MCU GPIOs without external level shifting. |
| Synchronous Buck Regulator | Communications Power Management |
|
Use Scenario: Main power stage in 48 V–12 V intermediate bus converters for 5G remote radio units. IC Role / Device Role / Timing Role: High-side or low-side switch paired with complementary MOSFET in synchronous buck controller IC. Use Value: 1.2 nC QGD and 3.1 K/W Rth(j-mb) suppress shoot-through risk and sustain 55 A continuous current with minimal heatsink area. |
Use Scenario: Power delivery in small-cell base station RF front-end bias supplies and envelope tracking circuits. IC Role / Device Role / Timing Role: Efficient switching element in multi-phase buck converters supplying FPGA and RFIC core voltages. Use Value: Avalanche rating (8.7 mJ) and 175 °C Tj max allow reliable operation under transient overloads common in burst-mode RF transmission. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSMN2R8-25YLH | Lower RDS(on) (2.8 mΩ @ 10 V), higher QG (14.2 nC), same 25 V rating and LFPAK56 package. | Better conduction loss but requires stronger gate driver; less suitable for space-constrained layouts due to larger LFPAK56 footprint. | Select when peak efficiency at high DC load dominates over gate drive capability and board area. |
| IRLML6344TRPBF | Higher RDS(on) (22 mΩ @ 4.5 V), smaller SOT-23 package, no avalanche rating, lower ID (4.3 A). | Limited to low-current (<5 A), low-power applications; lacks thermal robustness and transient resilience of PSMN9R0-25MLC. | Choose only for cost-sensitive, low-power signal switching where 25 V rating suffices but high current or ruggedness is unnecessary. |
Compared with PSMN2R8-25YLH and IRLML6344TRPBF, PSMN9R0-25MLC delivers optimal balance of low gate charge (5.4 nC), moderate on-resistance (9.8 mΩ @ 4.5 V), and proven avalanche ruggedness (8.7 mJ) in a compact LFPAK33 footprint-making it uniquely suited for mid-power industrial DC-DC and load switching where driver strength, thermal headroom, and fault tolerance are jointly critical.
Availability
PSMN9R0-25MLC is available at Aetrix Electronics and suitable for DC-to-DC converters, load switching, and synchronous buck regulators requiring stable component supply, consistent parametric performance, and long-term industrial lifecycle support.
Supply support for PSMN9R0-25MLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.
This device belongs to Nexperia's NextPower Superjunction MOSFET product line, engineered specifically for high-efficiency, high-frequency power conversion in space-constrained industrial and communications equipment.
FAQ
What is the maximum continuous drain current for PSMN9R0-25MLC at 100 °C mounting base temperature?
At Tmb = 100 °C and VGS = 10 V, the maximum continuous drain current is 39 A, as specified in Table 4 (Limiting Values). This derating reflects thermal constraints of the LFPAK33 package and must be validated against actual board layout and heatsinking conditions.
Does PSMN9R0-25MLC have an integrated body diode, and what are its key parameters?
Yes, it features a source-drain body diode with VSD = 0.83–1.1 V at IS = 15 A and Tj = 25 °C, reverse recovery time trr = 14.8 ns, and recovered charge Qr = 7.5 nC. These values support efficient synchronous rectification and fast freewheeling in buck topologies.
Can PSMN9R0-25MLC be used in avalanche mode, and what is its rated energy?
Yes-it is rated for non-repetitive unclamped avalanche with EAS = 8.7 mJ at Tj(init) = 25 °C, ID = 55 A, Vsup ≤ 25 V, and RGS = 50 Ω. This rating applies only to single-pulse events and requires careful layout to avoid secondary breakdown.
What is the gate threshold voltage range, and how does it vary with temperature?
VGS(th) ranges from 1.3 V to 1.95 V at Tj = 25 °C, with a temperature coefficient of –3.5 mV/K. This negative drift ensures stable turn-on behavior across –55 °C to 175 °C junction temperatures, critical for industrial ambient operation.
PSMN9R0-25MLC,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- SOT-1210, 8-LFPAK33 (5-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 25 V
- Current - Continuous Drain (Id) @ 25°C:
- 55A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 8.65mOhm @ 15A, 10V
- Vgs(th) (Max) @ Id:
- 1.95V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 11.7 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 705 pF @ 12.5 V
- FET Feature:
- -
- Power Dissipation (Max):
- 45W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- LFPAK33
PSMN9R0-25MLC,115 FAQ
1.How can I place an order for PSMN9R0-25MLC,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMN9R0-25MLC,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMN9R0-25MLC,115 reliable?
The price and inventory of PSMN9R0-25MLC,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMN9R0-25MLC,115 is usually 5 days.
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5.How can I obtain technical support or documentation for PSMN9R0-25MLC,115?
For technical support, including PSMN9R0-25MLC,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMN9R0-25MLC,115 requirements.
6.How does Aetrix verify that PSMN9R0-25MLC,115 is sourced from the original manufacturer or authorized distributors?
All PSMN9R0-25MLC,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMN9R0-25MLC,115 meets industry standards.
7.What is the process for return or replacement of PSMN9R0-25MLC,115?
All PSMN9R0-25MLC,115 units undergo pre-shipment inspection (PSI). If there is an issue with PSMN9R0-25MLC,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMN9R0-25MLC,115 part is unused and in its original packaging.
Return procedure for PSMN9R0-25MLC,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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