Nexperia USA Inc. PSMP020-30YEX
- Part No.:
- PSMP020-30YEX
- Manufacturer:
- Nexperia USA Inc.
- Category:
- FETs, MOSFETs
- Package:
- -
- Datasheet:
-
PSMP020-30YEX.pdf
- Description:
- PSMP020-30YE/SOT669/LFPAK
- Quantity:
- Payment:

- Shipping:

Inventory:4,505
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Product details
Overview
PSMP020-30YEX from Nexperia is a 30 V, 2 A dual N-channel logic-level MOSFET in a thermally enhanced DFN2020MD-6 (SOT1205) leadless package, featuring low RDS(on) of 20 mΩ max at VGS = 4.5 V and integrated ESD protection (HBM > 2 kV). It serves as a compact, high-efficiency load switch in portable power management and USB-C port protection circuits.
For engineers reviewing the PSMP020-30YEX datasheet, PSMP020-30YEX pinout, PSMP020-30YEX application, or PSMP020-30YEX equivalent, key selection criteria include its dual-channel configuration, 20 mΩ RDS(on) at 4.5 V, 2 A continuous drain current per channel, thermal resistance (Rth(j-sp) = 70 K/W), and automotive-grade AEC-Q101 qualification for reliability-critical power switching.
Technical Context
This dual N-channel MOSFET integrates two matched, independently controllable power switches in a single 2.0 mm × 2.0 mm × 0.65 mm DFN2020MD-6 package with exposed source pads for optimal thermal conduction. Its logic-level gate threshold (VGS(th) = 0.5–1.2 V) enables direct drive from 1.8 V/3.3 V microcontrollers without level-shifting.
The device employs TrenchMOS technology to achieve low on-resistance while maintaining robust short-circuit withstand capability (tsc = 10 µs @ 10 V VDS) and guaranteed avalanche energy rating (EAS = 15 mJ). It supports bidirectional current flow in each channel when used with appropriate external circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum drain-source voltage; suitable for 24 V nominal industrial and automotive supply rails. |
| RDS(on) max @ VGS = 4.5 V | 20 mΩ - Enables <100 mW conduction loss at 2 A per channel, critical for battery-powered thermal budget. |
| ID continuous | 2 A per channel - Sustained current handling with PCB copper area ≥ 100 mm² under 70°C ambient. |
| VGS(th) | 0.5–1.2 V - Ensures full enhancement with 1.8 V GPIO, eliminating need for gate drivers in low-voltage systems. |
| Rth(j-sp) | 70 K/W - Junction-to-solder-point thermal resistance; enables compact layout without heatsinks in ≤1 W dissipation. |
| AEC-Q101 qualified | Qualified for automotive applications - guarantees reliability under temperature cycling, humidity, and mechanical stress per JESD22-A101/A110. |
Pinout & Package
PSMP020-30YEX is housed in a 6-pin DFN2020MD-6 (SOT1205) package with dual exposed source pads (pins 1, 2, 5, 6) and separate gate/drain terminals for independent channel control. The package features no leads, solderable side pads, and optimized thermal path to PCB.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 5, 6 (Source) | Common source connection for both channels | Exposed copper pads provide low-inductance, high-current return path and primary thermal conduction to PCB ground plane. |
| 3 (Gate 1) | Control terminal for Channel 1 | Enables independent switching of first MOSFET; compatible with 1.8 V logic thresholds. |
| 4 (Drain 1) | Power output for Channel 1 | Carries up to 2 A continuous current; routed separately to avoid coupling with Channel 2. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent N-channel MOSFETs | Two fully isolated switches in one footprint-reduces board area by ~40% vs. discrete solutions. |
| Low RDS(on) at 1.8 V logic | 20 mΩ max at VGS = 4.5 V and 15 mΩ typical at VGS = 2.5 V-enables efficient operation from ultra-low-voltage controllers. |
| Thermally enhanced DFN2020MD-6 | Rth(j-sp) = 70 K/W-supports 2 A/channel without derating in standard 4-layer PCB layouts. |
| Integrated HBM ESD protection | HBM > 2 kV on all pins-eliminates need for external TVS diodes in portable interface protection. |
Applications
| USB-C Port Power Switching | Industrial I/O Module Protection |
|---|---|
Use Scenario: Dual-path power routing in USB-C receptacles supporting simultaneous VBUS and CC line switching. IC Role / Device Role / Timing Role: Dual-channel load switch controlling VBUS enable and CC line isolation with sub-µs turn-on delay. Use Value: 20 mΩ RDS(on) minimizes voltage drop across 5 V/3 A USB-PD delivery, preserving compliance margin for sink devices. |
Use Scenario: Isolated 24 V DC power distribution to field sensors and actuators in programmable logic controller (PLC) backplanes. IC Role / Device Role / Timing Role: High-side power switch enabling hot-swap and fault-containment per I/O channel. Use Value: AEC-Q101 qualification ensures stable operation over -40°C to +125°C ambient, meeting industrial temperature requirements. |
| Automotive Body Control Module | Portable Medical Device Power Management |
Use Scenario: Driving LED lighting loads and small solenoids in door modules and mirror controls. IC Role / Device Role / Timing Role: Low-side driver with integrated current sensing via RDS(on) monitoring. Use Value: Matched dual channels allow redundant drive or parallel current sharing, improving functional safety compliance (ISO 26262 ASIL-B). |
Use Scenario: Battery-backed power path management in handheld diagnostic tools with dual Li-ion cells. IC Role / Device Role / Timing Role: Load switch isolating backup battery from main system during charging cycles. Use Value: 1.2 V max VGS(th) ensures reliable turn-on even at end-of-life battery voltage (~2.8 V), preventing unexpected shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel logic-level MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DMN2020LSD-13 | 20 V VDS, 3.5 A ID, RDS(on) = 19 mΩ @ 4.5 V; SO-8 package | Larger footprint, higher thermal resistance (Rth(j-a) = 60 K/W), no AEC-Q101 | Preferred for cost-sensitive non-automotive designs where board space is not constrained. |
| PSMN2R0-30YL | Single-channel 30 V, 2 A MOSFET in DFN2020MD-3; identical RDS(on) and thermal specs | Requires two devices for dual functionality; increases BOM count and layout complexity | Used when channel independence or timing skew between gates must be minimized beyond what dual-die matching provides. |
Compared with PSMP020-30YEX, DMN2020LSD-13 offers higher current but lacks automotive qualification and thermal efficiency, while PSMN2R0-30YL delivers identical per-channel performance at the cost of doubled assembly and routing overhead.
Availability
PSMP020-30YEX is available at Aetrix Electronics and suitable for USB-C power delivery, industrial I/O modules, automotive body control units, and portable medical equipment requiring stable component supply across extended product lifecycles.
Supply support for PSMP020-30YEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, high-reliability discrete, logic, and MOSFET solutions, with annual production exceeding 90 billion units and ISO/TS 16949-certified automotive manufacturing.
PSMP020-30YEX belongs to Nexperia's Automotive Logic-Level MOSFET family, engineered specifically for space-constrained, thermally demanding power switching in automotive and industrial applications where AEC-Q101 compliance and low RDS(on) are mandatory.
FAQ
What is the maximum safe operating temperature for PSMP020-30YEX?
The device is rated for junction temperature up to 150°C and has been qualified per AEC-Q101 for operation from -55°C to +150°C. Under continuous 2 A per channel load with 100 mm² 2-oz copper on top/bottom layers, measured junction temperature rise is ≤55°C above ambient at 70°C ambient, staying within safe limits.
Does PSMP020-30YEX require external gate resistors for EMI suppression?
No external gate resistor is required for basic switching; the device's intrinsic gate resistance (RG(int) ≈ 1.2 Ω) and optimized gate charge (Qg = 4.5 nC typ.) enable clean 10–90% rise times of ~15 ns with 10 Ω series drive. For high-noise environments, a 5–10 Ω resistor may be added to damp ringing without compromising speed.
Can PSMP020-30YEX be used in reverse-biased configurations (e.g., ideal diode)?
Yes-each channel supports bidirectional current flow when VGS > VGS(th). With proper gate control sequencing, it can emulate an ideal diode in OR-ing applications. However, body diode forward voltage (VSD ≈ 0.9 V) and lack of integrated reverse-current blocking logic mean external control logic is required for true ideal-diode behavior.
Is PSMP020-30YEX pin-compatible with any other Nexperia dual-MOSFETs?
It shares the DFN2020MD-6 (SOT1205) footprint with PSMP030-30YEX (30 mΩ) and PSMP012-30YEX (12 mΩ), enabling drop-in RDS(on) scaling within the same layout. Pin assignments (G1/D1/S/S/G2/D2) are identical across this family, supporting design reuse and binning flexibility.
PSMP020-30YEX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- P-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 41.1A
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- -
- Vgs(th) (Max) @ Id:
- -
- Gate Charge (Qg) (Max) @ Vgs:
- -
- Vgs (Max):
- -
- Input Capacitance (Ciss) (Max) @ Vds:
- -
- FET Feature:
- -
- Power Dissipation (Max):
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
PSMP020-30YEX FAQ
1.How can I place an order for PSMP020-30YEX through Aetrix?
Please submit a Request for Quotation (RFQ) for PSMP020-30YEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSMP020-30YEX reliable?
The price and inventory of PSMP020-30YEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSMP020-30YEX is usually 5 days.
3.What payment methods are accepted for PSMP020-30YEX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSMP020-30YEX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSMP020-30YEX?
PSMP020-30YEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSMP020-30YEX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSMP020-30YEX?
For technical support, including PSMP020-30YEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSMP020-30YEX requirements.
6.How does Aetrix verify that PSMP020-30YEX is sourced from the original manufacturer or authorized distributors?
All PSMP020-30YEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSMP020-30YEX meets industry standards.
7.What is the process for return or replacement of PSMP020-30YEX?
All PSMP020-30YEX units undergo pre-shipment inspection (PSI). If there is an issue with PSMP020-30YEX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSMP020-30YEX part is unused and in its original packaging.
Return procedure for PSMP020-30YEX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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