Nexperia USA Inc. PXN6R2-25QLJ

Overview

PXN6R2-25QLJ from Nexperia is a 25 V, N-channel enhancement-mode Trench MOSFET in MLPAK33 (SOT8002-1) package, designed for low-side switching in power conversion and battery management. It delivers R_DS(on) = 5.3 mΩ @ V_GS = 10 V, 13.1 A, supports logic-level drive (V_GS(th) = 1.7 V typ), and features ultra-low Q_G = 8.1 nC and Q_GD = 2.2 nC for high-frequency DC–DC operation.

For engineers reviewing the PXN6R2-25QLJ datasheet, PXN6R2-25QLJ pinout, PXN6R2-25QLJ application, or PXN6R2-25QLJ equivalent, this device is selected for compact, thermally efficient low-voltage switching where gate charge minimization, soft-recovery diode behavior, and FR4-mountable thermal performance (R_th(j-sp) = 2.1 K/W) are critical.

Technical Context

This MOSFET employs Trench technology to achieve low on-resistance and fast switching with minimized ringing-enabled by optimized gate-drain charge (Q_GD) and reverse transfer capacitance (C_rss = 76 pF). Its source-drain diode exhibits t_rr = 15 ns and Q_r = 6 nC, supporting soft-recovery in synchronous rectification.

The device operates with V_GS = ±20 V absolute max, rated for continuous I_D = 13.1 A at T_amb = 25 °C (FR4, 6 cm² drain pad), and maintains R_DS(on) stability across T_j = 25–150 °C (1.5× increase), enabling robust thermal design in space-constrained PCB layouts.

Key Specifications

Pinout & Package

MLPAK33 (SOT8002-1) is a thermally enhanced 8-terminal surface-mount package measuring 3.3 × 3.3 × 0.8 mm, with exposed drain pads on terminals 5–8 and triple-source configuration (pins 1–3) for low-inductance source return.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel low-voltage switching applications.

Compared with BSC010N04LS6, PXN6R2-25QLJ trades 0.5 mΩ higher R_DS(on) for 30% lower Q_G and 40% smaller footprint; versus NTMFS4C09NT1G, it delivers tighter R_DS(on) tolerance and superior soft-recovery diode performance for noise-sensitive DC–DC stages.

Availability

PXN6R2-25QLJ is available at Aetrix Electronics and suitable for DC–DC conversion, battery management, and low-side load switching requiring stable component supply, consistent parametric performance, and long-term production continuity.

Supply support for PXN6R2-25QLJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors - high-volume, high-reliability discrete, logic, and MOSFET devices engineered for efficiency and miniaturization.

This device belongs to Nexperia's TrenchMOS logic-level portfolio, designed specifically for space-constrained, high-frequency power switching in consumer, computing, and industrial applications where thermal density and gate drive simplicity are critical.

FAQ

What is the maximum continuous drain current for PXN6R2-25QLJ at 100 °C ambient temperature?

The maximum continuous drain current is 8.3 A at T_amb = 100 °C with standard FR4 mounting (6 cm² drain pad). This value is derived from derating curves in Figure 2 of the datasheet and reflects thermal limits under steady-state conduction, not transient or pulse conditions.

Does PXN6R2-25QLJ have avalanche capability, and how is it specified?

Yes - it is rated for non-repetitive drain-source avalanche energy E_AS = 30 mJ at T_j(init) = 25 °C, I_D = 2.4 A, unclamped condition. This specification validates ruggedness against inductive switching transients but does not imply repetitive avalanche operation.

Can PXN6R2-25QLJ be used in a high-side switch configuration?

It is not recommended for high-side use without gate boosting. With V_GS limited to ±20 V and no integrated charge pump, achieving full enhancement above 15 V rail requires external level-shifting or bootstrap circuitry - its optimized characteristics target low-side and synchronous rectifier roles.

What is the recommended PCB layout for optimal thermal performance?

A 6 cm² tin-plated copper drain pad connected via ≥8 thermal vias (0.3 mm diameter, 0.8 mm pitch) to inner ground/power planes is specified in the datasheet. Source and gate traces should be short and wide to minimize inductance; the triple-source configuration supports symmetric current distribution in high-di/dt layouts.