STMicroelectronics SCTH35N65G2V-7

Overview

SCTH35N65G2V-7 from STMicroelectronics is a silicon carbide (SiC) N-channel power MOSFET in H²PAK-7 package, rated for 650 V V_DS, 67 mΩ R_DS(on) max at 20 V V_GS, and 45 A continuous drain current at T_C = 25 °C. It integrates a robust intrinsic SiC body diode and is engineered for high-efficiency, high-frequency switching in hard-switched topologies.

For engineers reviewing the SCTH35N65G2V-7 datasheet, SCTH35N65G2V-7 pinout, SCTH35N65G2V-7 application, or SCTH35N65G2V-7 equivalent, key selection criteria include its 73 nC total gate charge, 18 ns reverse recovery time, 3.3 V forward diode voltage at 20 A, and thermal resistance of 0.72 °C/W junction-to-case - all critical for PFC, LLC resonant, and industrial motor drive designs.

Technical Context

This device implements ST's second-generation SiC MOSFET process, delivering low on-resistance per unit area (55 mΩ typ.) and near-temperature-invariant switching loss. Its gate threshold voltage (1.8–5 V) and ±100 nA gate leakage support stable operation across -55 to 175 °C junction range.

The H²PAK-7 package enables dual-source configuration with dedicated driver source (Pin 2) and power source (Pins 3–7), reducing source inductance and improving gate control fidelity. The TAB serves as drain terminal, enabling low-inductance mounting and efficient heat extraction via direct thermal path.

Key Specifications

Pinout & Package

H²PAK-7 package: thermally enhanced surface-mount outline with isolated drain TAB (exposed copper pad), 7 signal terminals, and dual-source architecture for minimized common-source inductance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar SiC MOSFET switching applications.

Compared with C3M0065065K and IXFH40N65X2, SCTH35N65G2V-7 delivers lower gate charge and superior body diode metrics, making it optimal for high-frequency, bidirectional, and thermally constrained designs - especially where H²PAK-7's dual-source architecture improves system-level EMI and reliability.

Availability

SCTH35N65G2V-7 is available at Aetrix Electronics and suitable for industrial motor drives, renewable energy inverters, and EV onboard chargers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SCTH35N65G2V-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, with R&D and manufacturing operations across Europe, Asia, and the Americas.

This device belongs to ST's STPOWER SiC MOSFET product line, designed specifically for high-efficiency, high-power-density power conversion systems operating above 100 kHz and up to 175 °C junction temperature.

FAQ

What is the maximum recommended gate-source voltage for reliable operation?

The absolute maximum V_GS is -10 V to +22 V, but the recommended operating range is -5 V to +18 V per datasheet Table 1. Operating beyond +18 V risks accelerated gate oxide degradation, while negative bias below -5 V offers no additional benefit and may increase driver complexity. For robust noise immunity, -4 V to +15 V is commonly used in industrial designs.

Does the H²PAK-7 package require solder paste stencil modifications versus standard D²PAK?

Yes - the H²PAK-7 has a larger exposed drain TAB (10.0–10.4 mm × 7.4–7.6 mm) and tighter pitch (2.34–2.74 mm between pins). Recommended stencil aperture for the TAB is 80–90% area ratio with 125 µm thickness; pin apertures should match 0.5 mm pitch pads with 75% area ratio to prevent bridging on Pins 3–7.

Can SCTH35N65G2V-7 replace silicon IGBTs in existing 15 kW motor drives without redesign?

No - direct replacement requires gate drive voltage adjustment (SiC needs +15 V/-4 V vs. IGBT's +15 V/0 V), PCB layout revision to accommodate Kelvin source routing, and recalculation of snubber networks due to faster dV/dt (≥50 V/ns). Thermal interface must also be verified, as SiC shifts loss distribution toward conduction at high temperatures.

Is the intrinsic body diode suitable for continuous reverse conduction in totem-pole PFC?

Yes - the device's 18 ns t_rr, 7 A I_RRM, and low Q_rr (85 nC) are characterized for repetitive reverse conduction at 20 A and 175 °C. However, V_SD rises to ~4.1 V at 175 °C, increasing conduction loss; thermal design must ensure T_J remains ≤150 °C during sustained reverse current.