My Inquiry
My Account
Vishay Siliconix SI1413EDH-T1-GE3
- Part No.:
- SI1413EDH-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
SI1413EDH-T1-GE3.pdf
- Description:
- MOSFET P-CH 20V 2.3A SC70-6
- Quantity:
- Payment:
- Shipping:
Inventory:7,208
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI1413EDH-T1-GE3 from Vishay Siliconix is a P-channel enhancement-mode TrenchFET® power MOSFET rated for -20 V drain-source voltage, 0.115 Ω RDS(on) at -4.5 V gate drive, and -2.9 A continuous drain current at 25 °C - optimized for low-voltage load switching in space-constrained portable electronics.
For engineers reviewing the SI1413EDH-T1-GE3 datasheet, SI1413EDH-T1-GE3 pinout, SI1413EDH-T1-GE3 application, or SI1413EDH-T1-GE3 equivalent, key selection criteria include its thermally enhanced SC-70 (SOT-363) package, -1.8 V gate threshold compatibility with 1.8 V logic, ESD rating of 3000 V HBM, and halogen-free/RoHS-compliant construction.
Technical Context
This device operates as a single P-channel switch with gate-controlled conduction between source and drain terminals. Its trench-based silicon structure enables low on-resistance at low gate voltages, while the integrated body diode supports bidirectional current flow in level-shifting and reverse-polarity protection circuits.
The SC-70-6 package features three drain terminals (pins 1, 2, 4), one source (pin 5), and one gate (pin 3), enabling high-current capability and improved thermal dissipation over standard SOT-363 variants. Thermal resistance from junction to ambient is 100 °C/W (steady-state), validated per JEDEC JESD51-2A on 1" × 1" FR4 board.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | -20 V maximum drain-source voltage - supports operation across 3.3 V, 5 V, and 12 V rail systems with margin. |
| RDS(on) | 0.115 Ω at VGS = -4.5 V - enables <100 mW conduction loss at 2.9 A, critical for battery-powered efficiency. |
| ID (continuous) | -2.9 A at TA = 25 °C - sufficient for USB port power switches and RF PA bias control. |
| VGS(th) | -0.45 V typical threshold - ensures reliable turn-on with 1.8 V microcontroller GPIO without level shifting. |
| Qg | 5.6 nC typical total gate charge - reduces switching losses and driver power requirements in high-frequency PWM. |
| TJ range | -55 °C to +150 °C operating junction temperature - qualified for industrial and automotive under-hood ambient conditions. |
Pinout & Package
Package: SC-70 (SOT-363), thermally enhanced 6-lead surface-mount package with three paralleled drain terminals for reduced thermal resistance and higher current handling.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 4 | Drain (D) | Three internally connected drain terminals - reduce effective lead inductance and improve thermal path to PCB copper. |
| 3 | Gate (G) | Control input requiring ≤10 µA leakage at ±4.5 V - compatible with low-power MCU outputs. |
| 5 | Source (S) | Main current return path; tied to system ground or negative rail in high-side switch configurations. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® architecture | Enables 0.115 Ω RDS(on) at -4.5 V, reducing I²R losses by >30% vs. planar P-MOSFETs in same package. |
| Thermally enhanced SC-70 | Junction-to-foot thermal resistance of 34 °C/W - improves power handling by 2× over standard SOT-363 packages. |
| ESD protection | 3000 V HBM rating - eliminates need for external ESD clamps in handheld and wearable interface circuits. |
| Halogen-free & RoHS | Complies with IEC 61249-2-21 and Directive 2002/95/EC - meets environmental compliance for global OEM shipments. |
Applications
| USB Load Switching | RF Power Amplifier Switch |
|---|---|
Use Scenario: Controlled power delivery to USB peripheral ports with overcurrent and reverse-voltage protection. IC Role / Device Role / Timing Role: High-side P-channel load switch enabling hot-plug isolation and inrush current limiting. Use Value: Low RDS(on) minimizes voltage drop across VBUS, preserving 5 V regulation margin for downstream devices. |
Use Scenario: Bias enable/disable control for cellular or WiFi front-end power amplifiers during transmit/receive cycles. IC Role / Device Role / Timing Role: Fast-turning P-MOSFET switch controlling DC supply to PA core, synchronized with RF envelope timing. Use Value: 5.6 nC Qg allows sub-microsecond switching, minimizing PA bias transition time and improving spectral mask compliance. |
| Logic-Level Level Shifter | Reverse Polarity Protection |
Use Scenario: Translating 1.8 V GPIO signals to control 5 V or 12 V subsystems in mixed-voltage embedded systems. IC Role / Device Role / Timing Role: Gate-driven P-channel translator providing inverted logic-level translation with minimal propagation delay. Use Value: -0.45 V VGS(th) ensures full enhancement at 1.8 V drive, eliminating need for external pull-up resistors or charge pumps. |
Use Scenario: Preventing damage from accidental battery reversal in portable medical or instrumentation equipment. IC Role / Device Role / Timing Role: Source-connected P-MOSFET acting as ideal diode replacement in series with positive supply rail. Use Value: 0.115 Ω RDS(on) yields <300 mV forward drop at 2.5 A - 60% lower than Schottky diode solutions, improving battery runtime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar P-channel MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DMN2013LFG-7 | Lower RDS(on) (0.095 Ω @ -4.5 V) but larger SOT-23-3 package; no multi-drain configuration. | Lacks SC-70 thermal enhancement; unsuitable for high-density layouts requiring minimal footprint. | Prefer when lower on-resistance is prioritized over board area and thermal performance. |
| AO3413 | Higher RDS(on) (0.13 Ω @ -4.5 V); identical SC-70-6 pinout and marking code BA. | Same footprint and layout compatibility; slightly higher conduction loss in high-current loads. | Select when cost sensitivity outweighs marginal efficiency gain and thermal margin is adequate. |
Compared with DMN2013LFG-7 and AO3413, SI1413EDH-T1-GE3 delivers optimal balance of ultra-low gate threshold, triple-drain thermal design, and halogen-free compliance - making it preferred for compact, battery-critical, and environmentally regulated designs.
Availability
SI1413EDH-T1-GE3 is available at Aetrix Electronics and suitable for USB load switching, RF PA switching, logic-level translation, and reverse polarity protection requiring stable component supply and long-term industrial availability.
Supply support for SI1413EDH-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in MOSFETs, diodes, optoelectronics, and passive components with emphasis on power efficiency and reliability.
The Si1413EDH product line targets space-constrained, low-voltage power management applications where thermal performance, logic-level compatibility, and environmental compliance are mandatory design requirements.
FAQ
What is the maximum continuous drain current for SI1413EDH-T1-GE3 at 85 °C ambient?
The SI1413EDH-T1-GE3 supports -2.0 A continuous drain current at TA = 85 °C, as specified in the Absolute Maximum Ratings table. This derating reflects thermal limitations of the SC-70 package on standard FR4 PCBs and must be verified against actual board layout and airflow conditions in the final design.
Does SI1413EDH-T1-GE3 support 1.8 V logic-level gate drive?
Yes, SI1413EDH-T1-GE3 has a typical gate threshold voltage of -0.45 V and achieves 0.155 Ω RDS(on) at VGS = -2.5 V - confirming full enhancement with 1.8 V logic outputs. The device is explicitly rated as "1.8 V Rated" in Vishay's official documentation.
What is the thermal resistance from junction to ambient for SI1413EDH-T1-GE3?
The SI1413EDH-T1-GE3 has a maximum junction-to-ambient thermal resistance (RthJA) of 125 °C/W under steady-state conditions on a 1" × 1" FR4 board, per JEDEC JESD51-2A. Its typical value is 100 °C/W, and the junction-to-foot (RthJF) is 34 °C/W - critical for thermal modeling in high-reliability applications.
Is SI1413EDH-T1-GE3 pin-compatible with AO3413?
Yes, SI1413EDH-T1-GE3 shares identical SC-70-6 pinout, marking code (BA), and terminal assignments with AO3413. Both devices use pins 1/2/4 for drain, pin 3 for gate, and pin 5 for source - enabling direct layout reuse where thermal and RDS(on) requirements align.
What does the "-GE3" suffix indicate in SI1413EDH-T1-GE3?
The "-GE3" suffix in SI1413EDH-T1-GE3 denotes compliance with both RoHS Directive 2002/95/EC and halogen-free requirements per IEC 61249-2-21. It distinguishes this variant from the "-E3" version, which is RoHS-compliant but not halogen-free.
SI1413EDH-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- P-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 2.3A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 1.8V, 4.5V
- Rds On (Max) @ Id, Vgs:
- 115mOhm @ 2.9A, 4.5V
- Vgs(th) (Max) @ Id:
- 450mV @ 100µA (Min)
- Gate Charge (Qg) (Max) @ Vgs:
- 8 nC @ 4.5 V
- Vgs (Max):
- ±12V
- Input Capacitance (Ciss) (Max) @ Vds:
- -
- FET Feature:
- -
- Power Dissipation (Max):
- 1W (Ta)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-6
SI1413EDH-T1-GE3 FAQ
1.How can I place an order for SI1413EDH-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI1413EDH-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI1413EDH-T1-GE3 reliable?
The price and inventory of SI1413EDH-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI1413EDH-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SI1413EDH-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI1413EDH-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI1413EDH-T1-GE3?
SI1413EDH-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI1413EDH-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI1413EDH-T1-GE3?
For technical support, including SI1413EDH-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI1413EDH-T1-GE3 requirements.
6.How does Aetrix verify that SI1413EDH-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SI1413EDH-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI1413EDH-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SI1413EDH-T1-GE3?
All SI1413EDH-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SI1413EDH-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI1413EDH-T1-GE3 part is unused and in its original packaging.
Return procedure for SI1413EDH-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI1413EDH-T1-GE3 Tags
-
BSZ180P03NS3EGATMA1
Infineon Technologies
-
SIRA14DP-T1-GE3
Vishay Siliconix
-
AO4419
Alpha & Omega Semiconductor Inc.
-
SISA14BDN-T1-GE3
Vishay Siliconix
-
PSMN9R5-30YLC,115
Nexperia USA Inc.
-
BUK9Y21-40E,115
Nexperia USA Inc.
-
RTQ035N03HZGTR
Rohm Semiconductor
-
FDMS7680
onsemi
-
RQ3E180BNTB
Rohm Semiconductor
-
STL6N2VH5
STMicroelectronics
-
DMPH4029LFGQ-7
Diodes Incorporated
-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
