Vishay Siliconix SI5504BDC-T1-GE3
- Part No.:
- SI5504BDC-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FET, MOSFET Arrays
- Package:
- 8-SMD, Flat Leads
- Datasheet:
-
SI5504BDC-T1-GE3.pdf
- Description:
- MOSFET N/P-CH 30V 4A/3.7A 1206-8
- Quantity:
- Payment:

- Shipping:

Inventory:34,323
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5504BDC-T1-GE3 from Vishay Siliconix is a dual-channel, lead-free and halogen-free 1206-8 ChipFET® package N- and P-channel 30 V MOSFET pair. It delivers 4 A continuous drain current (N-ch) and −3.7 A (P-ch) at TC = 25 °C, with RDS(on) of 0.065 Ω @ VGS = 10 V (N-ch) and 0.140 Ω @ VGS = −10 V (P-ch), enabling compact DC/DC conversion and bidirectional load switching in portable power rails.
For engineers reviewing the SI5504BDC-T1-GE3 datasheet, SI5504BDC-T1-GE3 pinout, SI5504BDC-T1-GE3 application, or SI5504BDC-T1-GE3 equivalent, this dual-channel trench MOSFET supports space-constrained, low-voltage load switch and synchronous buck converter topologies requiring matched complementary channel performance, thermal efficiency on FR4 PCBs, and RoHS-compliant assembly.
Technical Context
The SI5504BDC-T1-GE3 integrates independent N- and P-channel TrenchFET® MOSFETs in a single 1206-8 ChipFET® package, sharing no internal connection between channels. Each channel features fully specified gate threshold voltage (VGS(th) = 1.5–3.0 V for N-ch; −1.5 to −3.0 V for P-ch), body diode recovery time (trr = 30 ns N-ch, 20 ns P-ch), and dynamic parameters including Qg = 4.5 nC (N-ch) and 4.5 nC (P-ch) at ±10 V drive.
Thermal design is enabled by junction-to-foot (RthJF) of 33 °C/W (typ.) per channel and junction-to-ambient (RthJA) of 70 °C/W (typ.) on a 1" × 1" FR4 board. The leadless construction exposes bare copper at drain terminals, optimized for bottom-side solder interconnection without requiring solder fillets at terminal tips.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V (N-ch), −30 V (P-ch): Supports 24 V rail switching and 30 V abs max input in portable DC/DC stages. |
| RDS(on) | 0.065 Ω @ VGS = 10 V (N-ch); 0.140 Ω @ VGS = −10 V (P-ch): Enables <150 mW conduction loss at 4 A load. |
| ID (continuous) | 4 A (N-ch), −3.7 A (P-ch) at TC = 25 °C: Sustains full-rated load in thermally managed PCB layouts. |
| Qg | 4.5 nC (N-ch), 4.5 nC (P-ch) @ ±10 V: Allows fast switching with low gate drive power in 1–2 MHz converters. |
| tr/tf | 12–20 ns rise/fall (N-ch), 10–15 ns (P-ch) @ 10 V drive: Supports high-frequency synchronous rectification with minimal overlap loss. |
| VSD | 0.8–1.2 V (N-ch), −0.8 to −1.2 V (P-ch) @ IS = 2.6 A / −2 A: Limits reverse conduction loss during dead-time in half-bridge configurations. |
| RthJA | 70 °C/W (typ.) on 1" × 1" FR4: Enables ~1.5 W steady-state dissipation before reaching 150 °C junction limit. |
Pinout & Package
The SI5504BDC-T1-GE3 uses the 1206-8 ChipFET® package (3.05 mm × 1.90 mm × 0.42 mm), a leadless surface-mount dual-channel outline compatible with standard 1206 passive footprints but engineered for power semiconductor thermal performance. Drain terminals are exposed copper on the bottom side; no plating is applied post-singulation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (S1) | N-channel source | Primary return path for N-ch current; connects directly to PCB ground plane for low-inductance layout. |
| 2 (G1) | N-channel gate | Control input for N-ch; requires ≥1.5 V to turn on, ≤3 V threshold ensures TTL/CMOS compatibility. |
| 3 (S2) | P-channel source | High-side reference node for P-ch; tied to VIN in high-side switch configurations. |
| 4 (G2) | P-channel gate | Inverted control input for P-ch; driven low to enable conduction; threshold −1.5 to −3.0 V. |
| 5, 6 (D1) | N-channel drain | Parallel-connected drain terminals; both must be soldered to maximize thermal conduction and current capacity. |
| 7, 8 (D2) | P-channel drain | Parallel-connected drain terminals; shared thermal path to PCB copper enhances power handling. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® process | Enables ultra-low RDS(on) in miniature 1206-8 footprint-0.065 Ω N-ch at 10 V drive without SO-8 area penalty. |
| Dual-channel complementary pairing | Matched VGS(th) and dynamic timing (td(on), tr) across N/P channels simplifies gate driver design for synchronous buck or H-bridge. |
| Junction-to-foot thermal resistance | 33 °C/W typical per channel: Matches SO-8 thermal performance while occupying only 20% of its board area. |
| Lead-free and halogen-free construction | Meets IPC/JEDEC J-STD-020D reflow profile and IEC 61249-2-21 compliance for green electronics manufacturing. |
| Body diode recovery | trr = 30 ns (N-ch), 20 ns (P-ch): Reduces switching loss and EMI in hard-switched topologies versus standard MOSFETs. |
Applications
| USB Power Delivery Switching | Portable Device Load Switch |
|---|---|
Use Scenario: Bidirectional 5–20 V USB PD power path management in smartphones and tablets, where input and output rails require controlled sequencing and reverse-current blocking. IC Role / Device Role / Timing Role: SI5504BDC-T1-GE3 acts as complementary high- and low-side switches controlling VBUS routing and isolation between Type-C ports and battery charging ICs. Use Value: Low RDS(on) minimizes voltage drop across 3 A load paths; matched N/P thresholds ensure precise dead-time control and prevent shoot-through during state transitions. |
Use Scenario: Independent ON/OFF control of subsystems (e.g., display backlight, camera module, audio codec) in wearables and handhelds to reduce standby leakage. IC Role / Device Role / Timing Role: SI5504BDC-T1-GE3 serves as dual independent load switches-one N-ch for low-side sinking, one P-ch for high-side sourcing-with separate gate enables. Use Value: 0.140 Ω P-ch RDS(on) limits dropout to <530 mV at 3.7 A, preserving system voltage margin; integrated body diodes support back-powering during hot-plug events. |
| Synchronous Buck Converter Topology | Industrial Sensor Node Power Sequencing |
Use Scenario: 12 V input to 3.3 V/1.8 V point-of-load regulation in compact IoT edge nodes, where efficiency and thermal density are critical. IC Role / Device Role / Timing Role: SI5504BDC-T1-GE3 implements the high-side (P-ch) and low-side (N-ch) power switches in a discrete synchronous buck stage driven by external controller. Use Value: 4.5 nC total gate charge per channel reduces driver losses; 30 ns body diode recovery cuts cross-conduction loss by >30% vs. standard MOSFETs at 1 MHz operation. |
Use Scenario: Controlled power-up/down sequencing of mixed-voltage sensor subsystems (e.g., 5 V analog front-end, 3.3 V digital logic, 1.2 V ADC core) in factory automation modules. IC Role / Device Role / Timing Role: SI5504BDC-T1-GE3 provides isolated, sequenced enable paths-N-ch for ground-referenced loads, P-ch for supply-referenced rails-with independent gate timing. Use Value: Guaranteed VGS(th) range (±1.5 to ±3.0 V) ensures reliable turn-on with standard GPIOs; 150 °C max junction rating supports extended operation in sealed enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel complementary MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si7157DP-T1-GE3 | Same 1206-8 package; N-ch RDS(on) = 0.022 Ω @ 10 V, P-ch = 0.045 Ω @ −10 V - lower on-resistance but higher Qg (12.5 nC). | Better for high-current, low-loss apps (>5 A); less suitable for high-frequency switching due to larger gate charge. | Select Si7157DP-T1-GE3 when conduction loss dominates; choose SI5504BDC-T1-GE3 when gate drive power or switching speed is prioritized. |
| DMN3028LSD-13 | SO-8 package; N-ch RDS(on) = 0.028 Ω, P-ch = 0.045 Ω @ 10 V; higher thermal mass but larger footprint (5.0 × 6.0 mm). | Preferred for high-power industrial designs where PCB area is available and heatsinking is enhanced via clip or thermal pad. | Choose DMN3028LSD-13 for >2 W continuous dissipation; SI5504BDC-T1-GE3 remains optimal for space-constrained portable designs. |
Compared with Si7157DP-T1-GE3 and DMN3028LSD-13, the SI5504BDC-T1-GE3 offers balanced trade-offs: moderate RDS(on) and low Qg in the smallest possible footprint, making it uniquely suited for thermally constrained, high-frequency portable power stages where board area is at a premium.
Availability
SI5504BDC-T1-GE3 is available at Aetrix Electronics and suitable for portable DC/DC conversion, bidirectional load switching, and synchronous buck regulator applications requiring stable component supply, RoHS-compliant assembly, and consistent thermal performance across production batches.
Supply support for SI5504BDC-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency and reliability.
The SI5504BDC-T1-GE3 belongs to Vishay's ChipFET® family-engineered to deliver SO-8-level power handling in 1206 passive footprints for space-critical portable and battery-powered systems.
FAQ
What is the maximum continuous drain current rating for each channel of the SI5504BDC-T1-GE3?
The SI5504BDC-T1-GE3 supports 4 A continuous drain current for the N-channel device and −3.7 A for the P-channel device at case temperature TC = 25 °C. Derating applies above 25 °C: at TC = 85 °C, ratings reduce to 3.8 A (N-ch) and −2.7 A (P-ch). These values assume proper PCB copper area and thermal management per Vishay AN812 guidelines.
Does the SI5504BDC-T1-GE3 require special rework or soldering processes due to its leadless ChipFET® package?
Yes-the SI5504BDC-T1-GE3 uses a leadless 1206-8 ChipFET® package with exposed copper drain terminals. Manual soldering with an iron is not recommended. Reflow soldering per JEDEC J-STD-020D is required, and rework must use precision hot-air tools with profile control to avoid delamination or thermal stress on the die attach. No solder fillet is required at drain tips.
Can the N-channel and P-channel sections of the SI5504BDC-T1-GE3 be used independently in different circuits on the same PCB?
Yes-the SI5504BDC-T1-GE3 contains two electrically isolated MOSFETs sharing only mechanical packaging. The N-channel (pins 1, 2, 5, 6) and P-channel (pins 3, 4, 7, 8) have no internal connection. They may be used in separate functions-for example, N-ch as a low-side switch and P-ch as a high-side load switch-with independent gate drive and power domain assignments.
What is the body diode forward voltage specification for the SI5504BDC-T1-GE3 under typical operating conditions?
The SI5504BDC-T1-GE3 specifies VSD = 0.8–1.2 V for the N-channel body diode and −0.8 to −1.2 V for the P-channel body diode, measured at IS = 2.6 A (N-ch) or −2 A (P-ch) with VGS = 0 V and TJ = 25 °C. These values remain stable across −55 °C to 125 °C junction temperature per typical characterization curves.
How does the thermal performance of the SI5504BDC-T1-GE3 compare to standard SO-8 MOSFETs?
The SI5504BDC-T1-GE3 achieves RthJA = 70 °C/W (typ.) on a 1" × 1" FR4 board-identical to many SO-8 MOSFETs-despite occupying only 20% of the board area. Its RthJF = 33 °C/W (typ.) matches SO-8 performance by leveraging short internal leads and direct drain-to-PCB copper conduction, enabling SO-8-equivalent power handling in ultra-compact layouts.
SI5504BDC-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- 8-SMD, Flat Leads
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Technology:
- MOSFET (Metal Oxide)
- Configuration:
- N and P-Channel
- FET Feature:
- Logic Level Gate
- Drain to Source Voltage (Vdss):
- 30V
- Current - Continuous Drain (Id) @ 25°C:
- 4A, 3.7A
- Rds On (Max) @ Id, Vgs:
- 65mOhm @ 3.1A, 10V
- Vgs(th) (Max) @ Id:
- 3V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 7nC @ 10V
- Input Capacitance (Ciss) (Max) @ Vds:
- 220pF @ 15V
- Power - Max:
- 3.12W, 3.1W
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 1206-8 ChipFET™
SI5504BDC-T1-GE3 FAQ
1.How can I place an order for SI5504BDC-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5504BDC-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5504BDC-T1-GE3 reliable?
The price and inventory of SI5504BDC-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5504BDC-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SI5504BDC-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5504BDC-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5504BDC-T1-GE3?
SI5504BDC-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5504BDC-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5504BDC-T1-GE3?
For technical support, including SI5504BDC-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5504BDC-T1-GE3 requirements.
6.How does Aetrix verify that SI5504BDC-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SI5504BDC-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5504BDC-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SI5504BDC-T1-GE3?
All SI5504BDC-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SI5504BDC-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5504BDC-T1-GE3 part is unused and in its original packaging.
Return procedure for SI5504BDC-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5504BDC-T1-GE3 Tags

-
SSM6N7002KFU,LF
Toshiba Semiconductor and Storage

-
2N7002DW-7-F
Diodes Incorporated

-
SSM6L56FE,LM
Toshiba Semiconductor and Storage

-
SSM6N37FU,LF
Toshiba Semiconductor and Storage

-
2N7002DWH6327XTSA1
Infineon Technologies

-
2N7002BKS,115
Nexperia USA Inc.

-
DMG1016UDW-7
Diodes Incorporated

-
UM6K33NTN
Rohm Semiconductor

-
DMG6602SVT-7
Diodes Incorporated

-
EM6K34T2CR
Rohm Semiconductor

-
UM6K34NTCN
Rohm Semiconductor

-
DMG6601LVT-7
Diodes Incorporated
Tech Hub
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

