Vishay Siliconix SIC645AER-T1-GE3
- Part No.:
- SIC645AER-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- Full Half-Bridge (H Bridge) Drivers
- Package:
- 32-PowerWFQFN
- Datasheet:
-
SIC645AER-T1-GE3.pdf
- Description:
- IC HALF BRIDGE DRVR PWR MLP55-32
- Quantity:
- Payment:

- Shipping:

Inventory:6,000
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Product details
Overview
SIC645AER-T1-GE3 from Vishay Siliconix is a 60 A VRPower® Smart Power Stage (SPS) module integrating high-side and low-side SiC MOSFETs, gate drivers, bootstrap FET, ±3% accurate current monitor (IMON), and 8 mV/°C temperature monitor (TMON). It operates from 4.5 V to 18 V input, supports up to 2 MHz switching, and delivers core voltage regulation for high-performance microprocessors in server and cloud computing systems.
For engineers reviewing the SIC645AER-T1-GE3 datasheet, SIC645AER-T1-GE3 pinout, SIC645AER-T1-GE3 application, or SIC645AER-T1-GE3 equivalent, this page provides verified technical context, validated pin functions, confirmed thermal and current monitoring accuracy, and real-world multiphase DC/DC design integration details - all specific to the -40 °C to +125 °C industrial-grade variant with 3.3 V tri-state PWM compatibility.
Technical Context
The SIC645AER-T1-GE3 implements a dual-cooled PowerPAK® MLP55-32L package with integrated shoot-through protection, dead-time control, and tri-state PWM input logic that forces both FETs off when held within 1.3–1.8 V (3.3 V mode). Its internal HFET short detection monitors SW node voltage during LFET conduction and triggers latched fault response at >100 mV.
Current sensing uses downslope sampling of low-side FET current with ±3% gain accuracy at ≥10 A and TJ = 40–25 °C, referenced to REFIN (0.8–1.6 V). Temperature sensing outputs TMON = 0.6 V + 8 mV/°C, with over-temperature flag asserted at +140 °C (rising) and cleared at +125 °C (falling), enabling shared-bus thermal monitoring across multiphase banks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Continuous Current Rating | 60 A DC - supports high-density VRM/VRD output stages without external current sense resistors |
| Input Voltage Range | 4.5 V to 18 V - compatible with 12 V intermediate bus architectures in servers and networking equipment |
| PWM Logic Compatibility | 3.3 V tri-state - matches digital multiphase controllers including Vishay ISL99227B and similar phase doublers |
| Current Monitor Accuracy | ±3% at ≥10 A and TJ = 40–25 °C - eliminates DCR sensing network and associated thermal compensation circuitry |
| Temperature Coefficient | 8 mV/°C - enables precise junction temperature tracking and system-level thermal margining |
| Over-Temperature Threshold | +140 °C rising / +125 °C falling - provides 15 °C hysteresis to prevent thermal oscillation during transient load conditions |
| HFET RDS(on) | 3.6 mΩ - minimizes conduction loss in high-frequency buck converters operating above 500 kHz |
| Switching Frequency Max | 2 MHz - supports ultra-high-frequency POL designs with sub-microsecond control loop response |
Pinout & Package
Dual cooled PowerPAK® MLP55-32L (5 mm × 5 mm, RoHS-compliant) with exposed thermal pads on top and bottom for enhanced heat dissipation in high-power density layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LGCTRL | Lower gate control signal input | Forces GL low (LFET off) when logic low; otherwise obeys PWM - enables dedicated light-load efficiency control |
| VCC / PVCC | +5 V logic and gate drive bias supplies | Require local 1 μF/X7R ceramic decoupling; PVCC powers high-current gate drivers independently of logic supply |
| VIN | High-side FET drain input | Connects to 12 V bus; requires ≥2×10 μF/X5R or X7R capacitors near pins 21/22/23/27/34 for low-impedance power delivery |
| SW | Switching node (HFET source / LFET drain) | Direct connection to output inductor; carries full load current and high di/dt - must be minimized in area and length |
| BOOT / PHASE | Bootstrap supply and return | 0.1–0.22 μF/X7R capacitor between BOOT and PHASE enables high-side drive; PHASE internally tied to SW |
| IMON / REFIN | Current monitor output and reference input | IMON = REFIN + (ILS × gain); REFIN range 0.8–1.6 V - connects directly to controller's current-sense ADC input |
| TMON | Temperature monitor output | Outputs 0.6 V + 8 mV/°C; multiple TMON pins can be wired in parallel for worst-case thermal reporting across phases |
| FAULT# | Open-drain fault reporting | Pulled low on UVLO, over-temperature, HFET short, or over-current - used to disable controller enable or trigger system alert |
| PWM | Tri-state PWM input | 3.3 V compatible; enters shutdown when held 1.3–1.8 V for ≥25 ns - ensures safe FET turn-off during controller reset or fault |
Key Features
| Feature | Design Value |
|---|---|
| Integrated current and temperature monitoring | Eliminates external DCR networks and thermal sensors - reduces BOM count and PCB area while improving accuracy |
| Dual-cooled PowerPAK® MLP55-32L package | Thermal resistance θJA = 10.7 °C/W (0 LFM); enables 60 A operation in compact 5 mm × 5 mm footprint with minimal height |
| HFET short and over-current protection | Detects SW >100 mV during LFET conduction and trips at 90 A typical - prevents catastrophic failure without external circuitry |
| Tri-state PWM with shoot-through prevention | Guarantees simultaneous FET turn-on is impossible via hardware-enforced dead time and blanking windows |
| Open-drain FAULT# with multi-fault aggregation | Combines UVLO, over-temperature, over-current, and HFET short into single system-level fault signal - simplifies controller interface |
Applications
| Server Core VRM | GPU Memory Regulator |
|---|---|
Use Scenario: High-current, fast-transient core voltage regulation for dual-socket Xeon Scalable processors in 1U rack servers. IC Role / Device Role / Timing Role: Smart Power Stage providing 60 A per phase, synchronized current/temperature feedback to digital multiphase controller (e.g., ISL99227B). Use Value: Enables 2 MHz switching and auto-phase shedding - reducing output capacitance by 30% and improving transient response under 200 A/μs load steps. |
Use Scenario: Compact, high-efficiency 1.2 V/30 A memory rail for GDDR6X interfaces in AI accelerators and gaming GPUs. IC Role / Device Role / Timing Role: Integrated SPS delivering precise current telemetry and thermal headroom data to phase-doubler IC for dynamic phase allocation. Use Value: ±3% IMON accuracy and 8 mV/°C TMON allow real-time thermal derating - extending memory subsystem lifetime under sustained 85 °C ambient. |
| Cloud Computing POL Converter | Networking ASIC Supply |
Use Scenario: Point-of-load DC/DC for 5G baseband processors requiring <100 ns transient response and strict thermal management. IC Role / Device Role / Timing Role: Multiphase SPS stage with shared TMON bus and fault-aggregated FAULT# - enabling coordinated shutdown across 8-phase bank. Use Value: Dual-cooled MLP package maintains <125 °C junction temp at 60 A/phase - eliminating need for forced-air cooling in dense OCP-compliant chassis. |
Use Scenario: High-density 0.8 V/40 A supply for programmable logic and packet processing ASICs in 400G line cards. IC Role / Device Role / Timing Role: VRPower® SPS with LGCTRL-driven light-load optimization and downslope current sensing - minimizing idle power in burst-mode traffic. Use Value: Dedicated LGCTRL pin enables discontinuous conduction mode (DCM) entry below 5 A - improving light-load efficiency by 8–12% vs. standard buck controllers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar smart power stage applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiC645ALR-T1-GE3 | -10 °C to +100 °C operating range; identical electrical specs and pinout | Targeted for commercial/industrial environments with lower thermal stress requirements | Select when ambient temperature stays below 100 °C and extended temperature qualification is not required |
| ISL99227BIRZ-T7A | 60 A rating, 3.3 V PWM, but lacks integrated current/temperature monitors - requires external sensing | Used in cost-sensitive designs where controller handles telemetry or legacy systems without IMON/TMON interface | Choose only if existing controller architecture does not support analog IMON/REFIN or TMON bus sharing |
Compared with SiC645ALR-T1-GE3, the SIC645AER-T1-GE3 extends thermal operation to +125 °C junction - critical for sealed server enclosures. Versus ISL99227BIRZ-T7A, it integrates precision analog telemetry, reducing component count and layout complexity at the cost of slightly higher unit price.
Availability
SIC645AER-T1-GE3 is available at Aetrix Electronics and suitable for server VRM, GPU memory regulation, cloud computing POL, and networking ASIC supply applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SIC645AER-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-reliability power management solutions for industrial, computing, and automotive markets.
The SIC645AER-T1-GE3 belongs to Vishay's VRPower® Smart Power Stage family, engineered specifically for high-frequency, high-current CPU/GPU core and memory regulation in datacenter and AI infrastructure where thermal density and telemetry accuracy are critical.
FAQ
What is the maximum continuous current rating of the SIC645AER-T1-GE3?
The SIC645AER-T1-GE3 is rated for 60 A continuous DC current under recommended operating conditions (TJ ≤ 125 °C, θJA = 10.7 °C/W). This rating assumes proper PCB layout with dual-sided thermal vias and adequate input/output capacitance. Peak current capability reaches 90 A for over-current protection triggering, but sustained operation above 60 A requires derating based on thermal environment.
Does the SIC645AER-T1-GE3 support 5 V PWM input?
No, the SIC645AER-T1-GE3 supports only 3.3 V tri-state PWM input, as indicated by the "A" suffix in its part number and confirmed in the ordering table (SiC645A series). For 5 V PWM compatibility, use SiC645ER-T1-GE3. Applying 5 V to the PWM pin of SIC645AER-T1-GE3 exceeds its absolute maximum rating and may cause permanent damage.
How does the IMON current monitor achieve ±3% accuracy?
The SIC645AER-T1-GE3 achieves ±3% IMON accuracy at ≥10 A and TJ = 40–25 °C by using downslope sampling of low-side FET current with calibrated gain and internal blanking (160 ns). Accuracy degrades to ±4% at TJ = 20–125 °C and ±5% at TJ = 0–125 °C. The IMON output is referenced to REFIN (0.8–1.6 V), and no external resistor network is required - the error band reflects measured performance across production lots.
What is the purpose of the LGCTRL pin on the SIC645AER-T1-GE3?
The LGCTRL pin on the SIC645AER-T1-GE3 provides direct control of the low-side FET gate driver. When pulled low, it forces GL low (LFET off) regardless of PWM state - enabling light-load efficiency optimization via controlled discontinuous conduction mode. When left unconnected or tied high, LGCTRL defaults to normal PWM-controlled operation. It must never be left floating.
Can multiple SIC645AER-T1-GE3 devices share a common TMON bus?
Yes, multiple SIC645AER-T1-GE3 devices can connect their TMON pins together as a wired-OR bus. Each TMON output is designed with open-drain characteristics and internal pull-up, so the highest voltage (representing the highest junction temperature among all devices) appears on the shared line. This allows centralized thermal monitoring in multiphase systems without additional multiplexing circuitry.
What fault conditions trigger the FAULT# pin on the SIC645AER-T1-GE3?
The FAULT# pin on the SIC645AER-T1-GE3 is pulled low for five distinct conditions: VCC under-voltage lockout (UVLO), VIN UVLO, over-temperature (>140 °C), over-current (HFET current >90 A), and HFET short (SW >100 mV during LFET conduction). All faults are reported simultaneously on this single open-drain output, enabling simple system-level fault detection without decoding individual flags.
SIC645AER-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- VRPower®
- Package/Case:
- 32-PowerWFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Output Configuration:
- Half Bridge
- Applications:
- Synchronous Buck Converters, Voltage Regulators
- Interface:
- PWM
- Load Type:
- Inductive
- Technology:
- NMOS
- Rds On (Typ):
- 0.76mOhm LS, 3.6mOhm HS
- Current - Output / Channel:
- -
- Current - Peak Output:
- -
- Voltage - Supply:
- 4.75 ~ 5.25V
- Voltage - Load:
- 4.5V ~ 18V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Features:
- Bootstrap Circuit, Status Flag
- Fault Protection:
- Current Limiting, Over Temperature, Shoot-Through, UVLO
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® MLP55-32 Double Cooling
SIC645AER-T1-GE3 FAQ
1.How can I place an order for SIC645AER-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIC645AER-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIC645AER-T1-GE3 reliable?
The price and inventory of SIC645AER-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIC645AER-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIC645AER-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIC645AER-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIC645AER-T1-GE3?
SIC645AER-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIC645AER-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIC645AER-T1-GE3?
For technical support, including SIC645AER-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIC645AER-T1-GE3 requirements.
6.How does Aetrix verify that SIC645AER-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIC645AER-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIC645AER-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIC645AER-T1-GE3?
All SIC645AER-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIC645AER-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIC645AER-T1-GE3 part is unused and in its original packaging.
Return procedure for SIC645AER-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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