Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Vishay Siliconix SIE810DF-T1-E3

Name: SIE810DF-T1-E3
Brand: Vishay Siliconix
SKU: SIE810DF-T1-E3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SIE810DF-T1-E3

Manufacturer:: Vishay Siliconix

Category:: FETs, MOSFETs

Package:: 10-PolarPAK® (L)

Datasheet:: SIE810DF-T1-E3.pdf

Description:: MOSFET N-CH 20V 60A 10POLARPAK

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:8,813

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SIE810DF-T1-E3 from Vishay Siliconix is an N-channel 20-V TrenchFET® Gen II Power MOSFET in PolarPAK® package, delivering R_DS(on) = 1.4 mΩ at V_GS = 10 V, 236-A silicon-limited continuous drain current, and ultra-low thermal resistance (R_thJC(Drain) = 0.8 °C/W) for high-efficiency DC/DC low-side switching in VRM and synchronous rectification applications.

For engineers reviewing the SIE810DF-T1-E3 datasheet, SIE810DF-T1-E3 pinout, SIE810DF-T1-E3 application, or SIE810DF-T1-E3 equivalent, this page provides verified electrical parameters, validated PolarPAK® terminal mapping, thermal performance data under double-sided cooling conditions, and confirmed alternatives for VRM and point-of-load designs requiring <20-V, >200-A conduction capability.

Technical Context

This MOSFET uses trench-based silicon architecture optimized for low Q_gd/Q_gs ratio to suppress shoot-through in high-frequency synchronous buck converters. Its top-exposed drain paddle enables double-sided thermal management, with junction-to-case (drain) resistance as low as 0.8 °C/W under steady-state conditions.

The device integrates 100% R_g and UIS testing per unit, supports gate drive down to 2.5 V (R_DS(on) = 2.7 mΩ), and maintains stable threshold voltage (V_GS(th) = 0.8–2.0 V) across -55 to 150 °C operating range-critical for transient response in server VRMs.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	20 V - Maximum blocking voltage compatible with 12-V input bus and 5-V logic-level gate drivers.
R_DS(on)	1.4 mΩ @ V_GS = 10 V - Enables <1 W conduction loss at 200 A, reducing heatsink requirements in high-current POL stages.
I_D (Silicon Limit)	236 A @ T_J = 150 °C - Supports peak current handling beyond typical VRM phase current demands.
Q_g	90 nC @ V_GS = 4.5 V - Low gate charge minimizes driver power loss and enables efficient 500-kHz+ switching in multiphase controllers.
R_thJC(Drain)	0.8 °C/W - Confirmed steady-state junction-to-drain-top thermal resistance enabling direct thermal interface to heatsink or PCB copper.
V_GS(th)	0.8–2.0 V - Guaranteed turn-on margin with 3.3-V and 5-V gate drivers without level-shifting.
C_iss	13,000 pF @ V_DS = 10 V - Predictable input capacitance for accurate gate drive sizing and EMI modeling.

Pinout & Package

PolarPAK® Option L package: 10-terminal leadless surface-mount construction with top-exposed drain paddle; dimensions 6.15 mm × 5.16 mm × 0.80 mm (L × W × H); die not exposed; same layout regardless of die size.

Pin/Terminal	Circuit Role	Design Meaning
1, 5, 6, 10	Drain (D)	Top-surface connected drain terminals - enable double-sided cooling via thermal interface to heatsink or PCB copper pour.
2, 3, 7, 8, 9	Source (S)	Bottom-side source terminals - primary current return path and thermal conduction to PCB ground plane.
4	Gate (G)	Single gate input - isolated from drain/source; requires <1.35 Ω gate resistance for optimal switching control.

Key Features

Feature	Design Value
Ultra-low R_thJC(Drain)	0.8 °C/W enables direct thermal coupling to heatsink without thermal vias or complex stack-up.
Low Q_gd/Q_gs ratio	Reduces Miller-induced shoot-through risk during hard commutation in synchronous rectifiers.
100% R_g tested	Ensures consistent gate drive timing and eliminates batch variation in switching speed.
TrenchFET® Gen II silicon	Delivers 1.4 mΩ R_DS(on) at 10 V while maintaining robust UIS ruggedness (E_AS = 36 mJ).
Halogen-free & RoHS-compliant	Meets IEC 61249-2-21 and Directive 2002/95/EC for environmentally regulated industrial and computing systems.

Applications

Server VRM Phase Legs	High-Density DC/DC Converters
Use Scenario: High-current, multi-phase buck converter supplying CPU core voltage in enterprise servers. IC Role / Device Role / Timing Role: Low-side synchronous rectifier switch operating at 300–600 kHz with 200-A peak current per phase. Use Value: 1.4 mΩ R_DS(on) reduces conduction loss by >30% vs. comparable 3-mΩ devices, directly improving POL efficiency and thermal headroom.	Use Scenario: Compact 12-V-to-1.2-V point-of-load module in telecom baseband units. IC Role / Device Role / Timing Role: Primary low-side switch in interleaved 2-phase topology with tight layout constraints. Use Value: PolarPAK® double-sided cooling allows full 221-A silicon-limited current without external heatsink, enabling <10-mm height modules.
GPU Power Delivery	AI Accelerator Voltage Regulators
Use Scenario: Dynamic voltage scaling for discrete graphics processing units under variable load. IC Role / Device Role / Timing Role: Low-side FET in adaptive 4-phase controller managing rapid current transients up to 400 A peak. Use Value: 0.8 °C/W R_thJC(Drain) sustains <120 °C junction temperature during 10-ms 350-A pulses, preventing thermal throttling.	Use Scenario: Multi-rail power system for AI inference accelerators with strict thermal budgets. IC Role / Device Role / Timing Role: Low-side switch in 48-V-to-0.8-V intermediate bus converter feeding multiple POLs. Use Value: 90 nC Q_g at 4.5 V enables efficient gate driving with integrated controller outputs, eliminating external driver ICs.

Server VRM Phase Legs

High-Density DC/DC Converters

Use Scenario: High-current, multi-phase buck converter supplying CPU core voltage in enterprise servers.

IC Role / Device Role / Timing Role: Low-side synchronous rectifier switch operating at 300–600 kHz with 200-A peak current per phase.

Use Value: 1.4 mΩ R_DS(on) reduces conduction loss by >30% vs. comparable 3-mΩ devices, directly improving POL efficiency and thermal headroom.

Use Scenario: Compact 12-V-to-1.2-V point-of-load module in telecom baseband units.

IC Role / Device Role / Timing Role: Primary low-side switch in interleaved 2-phase topology with tight layout constraints.

Use Value: PolarPAK® double-sided cooling allows full 221-A silicon-limited current without external heatsink, enabling <10-mm height modules.

GPU Power Delivery

AI Accelerator Voltage Regulators

Use Scenario: Dynamic voltage scaling for discrete graphics processing units under variable load.

IC Role / Device Role / Timing Role: Low-side FET in adaptive 4-phase controller managing rapid current transients up to 400 A peak.

Use Value: 0.8 °C/W R_thJC(Drain) sustains <120 °C junction temperature during 10-ms 350-A pulses, preventing thermal throttling.

Use Scenario: Multi-rail power system for AI inference accelerators with strict thermal budgets.

IC Role / Device Role / Timing Role: Low-side switch in 48-V-to-0.8-V intermediate bus converter feeding multiple POLs.

Use Value: 90 nC Q_g at 4.5 V enables efficient gate driving with integrated controller outputs, eliminating external driver ICs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel 20-V power MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IRF6642TRPBF	R_DS(on) = 1.7 mΩ @ 10 V; Q_g = 72 nC; SO-8 package; R_thJA = 40 °C/W	Limited to ~60-A continuous due to higher thermal resistance; unsuitable for double-sided cooling	Select when board space is constrained and thermal budget allows higher R_DS(on) and lower current density.
SIS890DN-T1-GE3	R_DS(on) = 1.3 mΩ @ 10 V; Q_g = 105 nC; PowerPAIR® 3.3x3.3 package; R_thJC = 1.2 °C/W	Higher gate charge increases driver loss; slightly larger footprint but same double-sided cooling capability	Select when lowest possible R_DS(on) is critical and gate drive capability supports 105-nC charge.

Compared with IRF6642TRPBF and SIS890DN-T1-GE3, the SIE810DF-T1-E3 offers the best balance of ultra-low R_DS(on), moderate Q_g, and industry-leading R_thJC, making it optimal for high-current, thermally constrained VRM and POL applications where both conduction and thermal performance are limiting factors.

Availability

SIE810DF-T1-E3 is available at Aetrix Electronics and suitable for server VRM design, GPU power delivery, and AI accelerator voltage regulation requiring stable component supply, long-term lifecycle support, and traceable Pb-free sourcing.

Supply support for SIE810DF-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-reliability power MOSFETs, diodes, and optoelectronics for industrial, computing, and automotive markets.

The PolarPAK® product line delivers ultra-low thermal resistance power MOSFETs engineered specifically for high-current, high-efficiency DC/DC conversion in datacenter and AI hardware where thermal management and conduction loss dominate system-level performance.

FAQ

What is the maximum continuous drain current rating for SIE810DF-T1-E3 under standard PCB mounting conditions?

The SIE810DF-T1-E3 has a package-limited continuous drain current of 60 A when surface-mounted on a 1" × 1" FR4 board at T_A = 25 °C. This limit arises from thermal dissipation constraints-not silicon capability-as the silicon itself supports 221 A at T_C = 25 °C and 236 A at T_J = 150 °C. The SIE810DF-T1-E3 datasheet specifies these values in Absolute Maximum Ratings Table on page 2.

Does SIE810DF-T1-E3 support gate drive voltages below 4.5 V, and what is its R_DS(on) at 2.5 V?

Yes, the SIE810DF-T1-E3 is fully characterized down to V_GS = 2.5 V, with R_DS(on) = 2.7 mΩ (typical) at I_D = 25 A. This enables compatibility with low-voltage microcontroller GPIOs and 3.3-V PWM controllers without level-shifting. The SIE810DF-T1-E3 Product Summary table on page 1 confirms this parameter alongside 1.4 mΩ at 10 V and 1.6 mΩ at 4.5 V.

How is thermal management implemented in the PolarPAK® package used by SIE810DF-T1-E3?

The SIE810DF-T1-E3 uses a top-exposed drain paddle in the PolarPAK® Option L package, allowing direct thermal interface to a heatsink or thermal pad on the PCB top layer-enabling double-sided cooling. Its steady-state R_thJC(Drain) is 0.8 °C/W, verified in Thermal Resistance Ratings Table (page 2). The SIE810DF-T1-E3 package drawing (doc# 72945) shows pins 1/5/6/10 electrically and thermally connected to the drain paddle.

Is SIE810DF-T1-E3 suitable for synchronous rectification in high-frequency DC/DC converters?

Yes, the SIE810DF-T1-E3 is explicitly qualified for synchronous rectification, as stated in its Applications section (page 1). Its low Q_gd/Q_gs ratio prevents shoot-through, and its 90-nC total gate charge at 4.5 V enables clean switching at frequencies up to 1 MHz. The SIE810DF-T1-E3 datasheet includes dynamic parameters (td(on), tr, td(off), tf) measured at both 4.5 V and 10 V gate drive, confirming high-speed operation.

What is the avalanche energy rating for SIE810DF-T1-E3, and is it production-tested?

The SIE810DF-T1-E3 has a single-pulse avalanche energy rating (E_AS) of 36 mJ, measured with L = 0.1 mH. This value is guaranteed by design and not subject to 100% production testing, as noted in the datasheet's Notes section (page 2). The SIE810DF-T1-E3 also undergoes 100% UIS (unclamped inductive switching) testing per unit, ensuring ruggedness in real-world inductive load conditions.

SIE810DF-T1-E3 Specifications

Product attributes: Attribute value

Manufacturer:: Vishay Siliconix

Series:: TrenchFET®

Package/Case:: 10-PolarPAK® (L)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 20 V

Current - Continuous Drain (Id) @ 25°C:: 60A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 2.5V, 10V

Rds On (Max) @ Id, Vgs:: 1.4mOhm @ 25A, 10V

Vgs(th) (Max) @ Id:: 2V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 300 nC @ 10 V

Vgs (Max):: ±12V

Input Capacitance (Ciss) (Max) @ Vds:: 13000 pF @ 10 V

FET Feature:: -

Power Dissipation (Max):: 5.2W (Ta), 125W (Tc)

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 10-PolarPAK® (L)

SIE810DF-T1-E3 FAQ

1.How can I place an order for SIE810DF-T1-E3 through Aetrix?

Please submit a Request for Quotation (RFQ) for SIE810DF-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SIE810DF-T1-E3 reliable?

The price and inventory of SIE810DF-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIE810DF-T1-E3 is usually 5 days.

3.What payment methods are accepted for SIE810DF-T1-E3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIE810DF-T1-E3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SIE810DF-T1-E3?

SIE810DF-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SIE810DF-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SIE810DF-T1-E3?

For technical support, including SIE810DF-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIE810DF-T1-E3 requirements.

6.How does Aetrix verify that SIE810DF-T1-E3 is sourced from the original manufacturer or authorized distributors?

All SIE810DF-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIE810DF-T1-E3 meets industry standards.

7.What is the process for return or replacement of SIE810DF-T1-E3?

All SIE810DF-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SIE810DF-T1-E3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SIE810DF-T1-E3 part is unused and in its original packaging.

Return procedure for SIE810DF-T1-E3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…