Toshiba Semiconductor and Storage SSM10N954L,EFF
- Part No.:
- SSM10N954L,EFF
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- FETs, MOSFETs
- Package:
- 10-SMD, No Lead
- Datasheet:
-
SSM10N954L,EFF.pdf
- Description:
- COMMON-DRAIN NCH MOSFET, 12V, 13
- Quantity:
- Payment:

- Shipping:

Inventory:9,865
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SSM10N954L from Toshiba Electronic Devices & Storage Corporation is a silicon N-channel MOSFET designed for high-efficiency battery protection circuits, featuring 12 V source-source breakdown voltage, 2.1 mΩ typical RSS(ON) at VGS = 4.5 V, and 13.5 A DC source current rating. It operates in low-voltage Li-ion pack charge/discharge control with integrated body diode and RoHS/halogen-free compliance.
For engineers reviewing the SSM10N954L datasheet, SSM10N954L pinout, SSM10N954L application, or SSM10N954L equivalent, key selection criteria include its TCSPAC-153001 package thermal performance, gate threshold voltage (1.55–2.75 V), safe operating area under pulsed conditions, and electrostatic discharge sensitivity requiring strict handling protocols.
Technical Context
This MOSFET implements a single N-channel enhancement-mode structure optimized for bidirectional current flow in battery cell monitoring and overcurrent cutoff paths. Its low 2.2 mΩ RSS(ON) at 3.8 V gate drive enables efficient operation in compact portable power systems where gate drive voltage is constrained by battery voltage sag.
The device uses a source-source configuration (not drain-source) with symmetrical terminal roles, supporting reverse conduction via an integrated body diode (VF(S-S) = 0.8 V typ. at 6 A). Absolute maximum ratings specify 135 A pulsed source current (t ≤ 10 µs) and 150 °C channel temperature limit under defined PCB thermal conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V(BR)SSS | 12 V - Maximum sustainable source-source voltage before avalanche breakdown; defines upper limit for Li-ion battery stack voltage compatibility. |
| RSS(ON) @ VGS = 4.5 V | 2.1 mΩ (typ.) - Enables <100 mW conduction loss at 7 A, critical for thermal management in sealed battery packs. |
| IS (DC) | 13.5 A - Continuous source current rating at Ta = 25 °C on specified FR4 board; sets baseline for PCB copper area and fusing requirements. |
| Vth | 1.55–2.75 V - Gate threshold range ensures reliable turn-on with standard 3.3 V or 4.5 V microcontroller GPIOs without level-shifting. |
| Qg | 34 nC (typ.) - Total gate charge determines required driver strength and switching loss in high-frequency protection logic (e.g., 10–100 kHz). |
| VF(S-S) | 0.8 V (typ. at 6 A) - Forward voltage of integrated body diode enables passive reverse-current path during cell balancing or fault recovery. |
Pinout & Package
SSM10N954L is housed in the TCSPAC-153001 surface-mount package - a 3-terminal, symmetrical source-source configuration with no drain terminal exposed; terminals are labeled Source 1, Source 2, and Gate. The package measures 1.5 mm × 3.0 mm × 0.1 mm (typ.) and weighs 1.499 mg.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Source 1 | Current input/output terminal | Electrically identical to Source 2; bidirectional conduction path for battery protection FET switching. |
| Source 2 | Current input/output terminal | Paired with Source 1 to form symmetrical source-source switch; no intrinsic drain node - device functions as back-to-back MOSFET equivalent. |
| Gate | Control electrode | Receives voltage referenced to either source terminal; threshold behavior defined relative to local source potential. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low RSS(ON) | 2.1 mΩ at 4.5 V gate drive reduces I²R losses in high-current battery cutoff paths, extending thermal margin in space-constrained packs. |
| Source-source topology | Eliminates need for external series diodes or dual-MOSFET configurations in bidirectional protection, simplifying layout and BOM count. |
| ESD-sensitive design | Requires anti-static handling per JEDEC JS-001; gate oxide integrity depends on controlled workbench grounding and ionized air environments. |
| RoHS & halogen-free | Complies with EU Directive 2011/65/EU and halogen-free manufacturing standards, supporting environmental compliance for consumer electronics. |
Applications
| Lithium-ion Battery Pack Protection | Smart Power Bank Management |
|---|---|
Use Scenario: Integrated into secondary protection IC circuits to cut off charging/discharging paths during overcurrent, short-circuit, or overtemperature events. IC Role / Device Role / Timing Role: Acts as main current-blocking switch with sub-millisecond response enabled by low Qg and fast td(off) (5.3 µs). Use Value: Prevents thermal runaway by limiting fault current to <135 A for ≤10 µs while maintaining <2.2 mΩ on-state resistance during normal operation. | Use Scenario: Embedded in multi-cell portable power banks to enable independent cell-level cutoff and reverse-current blocking during USB-C PD negotiation. IC Role / Device Role / Timing Role: Functions as bidirectional isolation switch between battery cells and load/charger ports, leveraging symmetrical source-source conduction. Use Value: Eliminates need for discrete Schottky diodes or dual-N-channel layouts, reducing footprint by >40% and improving efficiency by 0.8% at 5 A load. |
| Wireless Earbud Battery Safety | Medical Wearable Energy Control |
Use Scenario: Used in ultra-compact true wireless stereo (TWS) earbuds to enforce strict current limits during rapid charge cycles and accidental shorting of micro-USB/USB-C contacts. IC Role / Device Role / Timing Role: Serves as primary overcurrent shutoff element triggered by fuel gauge IC alerts, with gate driven directly from 3.3 V system rail. Use Value: Enables reliable turn-on at VGS ≥ 3.3 V (within Vth range) and maintains <100 mW dissipation at peak 7 A discharge current. | Use Scenario: Deployed in Class II medical wearables (e.g., glucose monitors) to isolate battery from sensor subsystems during firmware updates or diagnostic mode entry. IC Role / Device Role / Timing Role: Provides fail-safe power gating with guaranteed 12 V withstand capability and 150 °C channel temperature rating for sterilization-cycle survivability. Use Value: Meets IEC 60601-1 creepage/clearance requirements via TCSPAC-153001's 0.1 mm profile and certified halogen-free molding compound. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar battery protection MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TSD10N954L | Same die, identical RSS(ON), V(BR)SSS, and Qg; differs only in marking and traceability documentation. | No functional difference; used interchangeably in Toshiba production lines for different customer traceability requirements. | Select SSM10N954L when full compliance documentation (Rev.5.0.A) and RoHS/halogen-free certification are contractually mandated. |
| AOB10N954L | Higher RSS(ON) (3.0 mΩ @ 4.5 V), larger 2.0×2.5 mm package, and 100 A pulsed rating; lacks explicit source-source topology labeling. | Requires PCB layout revision due to different footprint and thermal pad; suitable for higher-power industrial battery modules but not drop-in for TCSPAC-153001 footprints. | Choose AOB10N954L only if higher pulsed current headroom is needed and board redesign is acceptable. |
Compared with TSD10N954L, SSM10N954L offers identical electrical performance with enhanced documentation traceability; versus AOB10N954L, it provides superior thermal density and smaller footprint for space-critical wearables but lower absolute pulsed current capability.
Availability
SSM10N954L is available at Aetrix Electronics and suitable for lithium-ion battery protection, portable power bank safety, and medical wearable energy control requiring stable component supply, long-term lifecycle support, and halogen-free compliance.
Supply support for SSM10N954L includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs and manufactures discrete semiconductors, power devices, and storage solutions with emphasis on reliability, miniaturization, and environmental compliance.
The SSM10N954L belongs to Toshiba's TCSPAC-series source-source MOSFET product line, engineered specifically for compact, high-reliability battery protection in consumer and medical portable electronics.
FAQ
What is the maximum continuous source current rating for SSM10N954L?
The SSM10N954L has a DC source current rating of 13.5 A at Ta = 25 °C when mounted on a specified 25 mm × 27.5 mm FR4 board with 407 mm² copper area. This rating assumes proper thermal management; derating is required above 25 °C ambient or with reduced copper area. The SSM10N954L datasheet specifies that exceeding this current continuously risks accelerated parametric shift and reduced lifetime.
Does SSM10N954L support bidirectional current flow?
Yes, the SSM10N954L supports bidirectional current flow due to its source-source topology and symmetrical terminal construction. Both source terminals are electrically identical, enabling conduction in either direction when the gate is biased above threshold relative to the local source. The integrated body diode (VF(S-S) = 0.8 V typ.) further supports reverse conduction, making the SSM10N954L suitable for battery protection circuits requiring reverse-current blocking and recovery.
What is the gate threshold voltage range for SSM10N954L?
The gate threshold voltage (Vth) for SSM10N954L is specified from 1.55 V (min) to 2.75 V (max) at IS = 1.11 mA. This range ensures compatibility with 3.3 V and 4.5 V logic-level microcontrollers without external level shifting. The SSM10N954L must be driven with VGS > Vth for reliable turn-on and VGS < Vth for guaranteed turn-off, as defined in Toshiba's application notes for battery protection FETs.
Is SSM10N954L compatible with lead-free reflow soldering processes?
Yes, the SSM10N954L is qualified for lead-free reflow soldering per J-STD-020. Its TCSPAC-153001 package uses halogen-free molding compound and RoHS-compliant terminations, supporting peak reflow temperatures up to 260 °C. The SSM10N954L datasheet confirms moisture sensitivity level (MSL) 1 rating, meaning floor life is unlimited under dry-bag storage, and no baking is required prior to assembly.
How does the SSM10N954L differ from standard drain-source N-channel MOSFETs?
The SSM10N954L differs fundamentally by using a source-source configuration instead of drain-source, eliminating the drain terminal entirely. This architecture enables true bidirectional blocking and conduction without external diodes or dual-FET arrangements. Unlike conventional N-channel MOSFETs, the SSM10N954L's terminals are functionally symmetric, and its safe operating area is defined around source-source voltage (VSSS) rather than VDS. This makes the SSM10N954L uniquely suited for battery cell-level protection where polarity reversal and compact layout are critical.
SSM10N954L,EFF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- -
- Package/Case:
- 10-SMD, No Lead
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 12 V
- Current - Continuous Drain (Id) @ 25°C:
- 13.5A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 2.5V, 4.5V
- Rds On (Max) @ Id, Vgs:
- 2.75mOhm @ 6A, 4.5V
- Vgs(th) (Max) @ Id:
- 1.4V @ 1.11mA
- Gate Charge (Qg) (Max) @ Vgs:
- 25 nC @ 4 V
- Vgs (Max):
- ±8V
- Input Capacitance (Ciss) (Max) @ Vds:
- -
- FET Feature:
- -
- Power Dissipation (Max):
- 800mW (Ta)
- Operating Temperature:
- 150°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- TCSPAC-153001
SSM10N954L,EFF FAQ
1.How can I place an order for SSM10N954L,EFF through Aetrix?
Please submit a Request for Quotation (RFQ) for SSM10N954L,EFF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SSM10N954L,EFF reliable?
The price and inventory of SSM10N954L,EFF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SSM10N954L,EFF is usually 5 days.
3.What payment methods are accepted for SSM10N954L,EFF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SSM10N954L,EFF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SSM10N954L,EFF?
SSM10N954L,EFF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SSM10N954L,EFF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SSM10N954L,EFF?
For technical support, including SSM10N954L,EFF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SSM10N954L,EFF requirements.
6.How does Aetrix verify that SSM10N954L,EFF is sourced from the original manufacturer or authorized distributors?
All SSM10N954L,EFF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SSM10N954L,EFF meets industry standards.
7.What is the process for return or replacement of SSM10N954L,EFF?
All SSM10N954L,EFF units undergo pre-shipment inspection (PSI). If there is an issue with SSM10N954L,EFF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SSM10N954L,EFF part is unused and in its original packaging.
Return procedure for SSM10N954L,EFF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SSM10N954L,EFF Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

