Toshiba Semiconductor and Storage SSM3J112TU,LF
- Part No.:
- SSM3J112TU,LF
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- FETs, MOSFETs
- Package:
- 3-SMD, Flat Leads
- Datasheet:
-
SSM3J112TU,LF.pdf
- Description:
- MOSFET P-CH 30V 1.1A UFM
- Quantity:
- Payment:

- Shipping:

Inventory:8,968
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SSM3J112TU from Toshiba is a silicon P-channel enhancement-mode MOSFET designed for high-speed switching in low-voltage DC-DC converters, load switches, and battery protection circuits. It features 4 V gate drive capability, maximum on-resistance of 790 mΩ at VGS = −4 V, −30 V drain-source breakdown voltage, and 1.1 A continuous drain current rating.
For engineers reviewing the SSM3J112TU datasheet, SSM3J112TU pinout, SSM3J112TU application, or SSM3J112TU equivalent, this page delivers verified electrical parameters, thermal derating guidance for FR4 and ceramic mounting, switching timing data (ton = 14 ns, toff = 8.5 ns), and real-world design constraints including Vth range (−0.8 to −1.8 V) and Ciss/Coss values.
Technical Context
This device operates as a single P-channel power switch in common-source configuration with gate-controlled turn-on/turn-off. Its threshold voltage (Vth = −0.8 to −1.8 V) ensures reliable enhancement-mode behavior, while low input capacitance (Ciss = 86 pF) and fast switching times support operation up to several MHz in synchronous buck topologies.
The SSM3J112TU exhibits strong temperature-dependent RDS(on) behavior-rising from 390 mΩ at 25°C to ~0.8 Ω at 125°C under −4 V drive-and requires careful thermal management due to its 500 mW FR4-rated power dissipation limit and 150°C channel temperature maximum.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | −30 V: Maximum blocking voltage in reverse-biased drain-source path; defines safe operating range in 24 V systems. |
| RDS(on) max | 790 mΩ @ VGS = −4 V: Determines conduction loss and I²R heating in 4 V logic-driven applications. |
| ID (DC) | −1.1 A: Continuous current handling capacity with proper PCB copper area (645 mm² on FR4). |
| ton/toff | 14 ns / 8.5 ns: Enables efficient switching above 1 MHz in compact DC-DC regulators. |
| Ciss | 86 pF: Governs gate drive strength requirement and impacts EMI profile during transitions. |
| Vth | −0.8 to −1.8 V: Specifies minimum gate overdrive needed to ensure full enhancement; critical for 3.3 V/5 V control compatibility. |
| PD (FR4) | 500 mW: Thermal limit requiring trace width and copper pour design per JEDEC standards. |
Pinout & Package
SSM3J112TU uses the UFM (Ultra Small Flat) package: 2.1 mm × 1.7 mm × 0.7 mm, 3-pin surface-mount, tape-and-reel format. Weight: 6.6 mg (typ.).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (Gate) | Control electrode | Accepts negative VGS to modulate channel conductivity; requires ESD-safe handling and gate resistor (RG = 10 Ω typical) for controlled switching. |
| 2 (Source) | Reference node | Connected to system ground or higher potential rail in high-side switch configurations; serves as return path for gate drive current. |
| 3 (Drain) | Power output terminal | Carries switched load current; must be routed with adequate copper area to manage 1.1 A and thermal rise. |
Key Features
| Feature | Design Value |
|---|---|
| 4 V gate drive compatibility | Enables direct interface with 3.3 V and 5 V microcontrollers without level-shifting circuitry. |
| Low RDS(on) at −4 V | Reduces conduction losses in battery-powered systems where gate voltage is limited by cell count. |
| Fast switching (ton + toff < 25 ns) | Minimizes transition losses in high-frequency DC-DC converters, improving efficiency above 500 kHz. |
| Ultra-compact UFM package | Supports space-constrained designs such as wearables and IoT sensors with minimal PCB footprint (3.57 mm²). |
| JEITA-compliant marking | Ensures traceability and authenticity via standardized top-side laser marking (TOSHIBA 2-2U1A). |
Applications
| Battery Protection Circuit | USB Port Power Switch |
|---|---|
Use Scenario: Reverse-current blocking and overcurrent shutdown in single-cell Li-ion battery packs. IC Role / Device Role / Timing Role: P-channel MOSFET used as back-to-back switch to prevent battery discharge through USB VBUS when host is off. Use Value: Low 790 mΩ RDS(on) at −4 V minimizes voltage drop across protection FET, preserving usable battery capacity. | Use Scenario: Controlled 5 V power delivery to downstream USB peripherals in portable hubs or docking stations. IC Role / Device Role / Timing Role: High-side load switch enabling/disabling VBUS with microcontroller GPIO. Use Value: Fast 14 ns turn-on time ensures rapid power-up response (<100 µs) meeting USB enumeration timing requirements. |
| DC-DC Synchronous Buck High-Side Switch | LED Dimming Driver |
Use Scenario: Upper switch in non-isolated 12 V → 3.3 V buck converter for industrial sensor nodes. IC Role / Device Role / Timing Role: P-channel MOSFET driven by integrated gate driver IC to replace external N-channel + level shifter. Use Value: 86 pF Ciss reduces gate charge demand, lowering driver IC power consumption and heat generation. | Use Scenario: PWM-controlled current sink for monochrome LED backlighting in medical display panels. IC Role / Device Role / Timing Role: Low-side switch (source grounded) modulating LED current at 1–10 kHz. Use Value: −1.8 V maximum Vth ensures full turn-on even with aging MCU outputs or voltage droop on 3.3 V rails. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar P-channel MOSFET switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DMN2011UFG-7 | RDS(on) = 500 mΩ @ −4.5 V; slightly lower VDS (−20 V); 1.2 A ID; SOT-23 package | Lower voltage rating limits use in 24 V systems; better suited for 5 V logic-controlled 12 V loads | Select when gate drive is ≥ −4.5 V and system voltage ≤ 20 V; verify thermal margin on FR4 with reduced RDS(on). |
| AO3415 | RDS(on) = 550 mΩ @ −4.5 V; −20 V VDS; 4 A ID; SOT-23 package | Higher current rating but same voltage class; larger die increases gate charge (Qg = 4.2 nC vs. SSM3J112TU's ~2.5 nC) | Prefer for higher-current 5 V–12 V loads where faster switching is less critical than conduction loss reduction. |
Compared with DMN2011UFG-7 and AO3415, the SSM3J112TU offers superior −30 V blocking capability and tighter Vth distribution for stable 3.3 V–4 V drive, making it optimal for space-constrained 24 V industrial interfaces where reliability at elevated ambient temperatures matters.
Availability
SSM3J112TU is available at Aetrix Electronics and suitable for battery protection circuits, USB power switches, DC-DC synchronous buck high-side switches, and LED dimming drivers requiring stable component supply and long-term industrial availability.
Supply support for SSM3J112TU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation is a Japanese semiconductor manufacturer specializing in discrete power devices, analog ICs, and memory solutions with global automotive and industrial certifications.
The SSM3J series targets ultra-compact, low-voltage P-channel MOSFET applications where board space, gate drive simplicity, and thermal performance in thin-profile packages are critical design priorities.
FAQ
What is the maximum continuous drain current rating for SSM3J112TU?
The SSM3J112TU has a maximum continuous drain current (ID) of −1.1 A at Ta = 25°C when mounted on an FR4 board with 645 mm² copper pad. This rating decreases with rising ambient temperature and must be derated per the PD–Ta curve in the datasheet; at 85°C, the practical limit drops to approximately −0.7 A.
Can SSM3J112TU be driven directly from a 3.3 V microcontroller GPIO?
Yes - the SSM3J112TU is specifically characterized for 4 V gate drive, and its Vth range (−0.8 to −1.8 V) ensures reliable turn-on with 3.3 V logic when referenced to a negative gate voltage (e.g., source at 3.3 V, gate at 0 V). However, RDS(on) will be higher (~790 mΩ) than at −10 V, so conduction loss must be validated for the target load current.
What is the thermal resistance (RthJA) of SSM3J112TU on FR4?
The SSM3J112TU has a junction-to-ambient thermal resistance (RthJA) of 250°C/W when mounted on a standard FR4 board (25.4 mm × 25.4 mm × 1.6 mm, 645 mm² Cu pad). This value rises significantly with smaller copper areas - e.g., to ~400°C/W with minimal 0.45 mm × 0.8 mm × 3 Cu traces - requiring layout verification for sustained >0.5 A operation.
Does SSM3J112TU support avalanche energy rating?
No - the SSM3J112TU datasheet does not specify unclamped inductive switching (UIS) or single-pulse avalanche energy (EAS) ratings. It is not rated for repetitive or unclamped inductive load switching; external clamping (e.g., TVS diode or RCD snubber) is required in relay or solenoid drive applications to avoid catastrophic failure.
What is the gate charge (Qg) specification for SSM3J112TU?
The SSM3J112TU does not publish a total gate charge (Qg) value in its official datasheet. However, based on Ciss = 86 pF and typical gate threshold behavior, estimated Qg is ~2.5 nC at VGS = −10 V. For precise driver sizing, designers should refer to the dynamic input characteristic curves and use gate resistance (RG = 10 Ω) test conditions from the switching time section.
SSM3J112TU,LF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- -
- Package/Case:
- 3-SMD, Flat Leads
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- P-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 1.1A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 4V, 10V
- Rds On (Max) @ Id, Vgs:
- 390mOhm @ 500mA, 10V
- Vgs(th) (Max) @ Id:
- 1.8V @ 100µA
- Gate Charge (Qg) (Max) @ Vgs:
- -
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 86 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 800mW (Ta)
- Operating Temperature:
- 150°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- UFM
SSM3J112TU,LF FAQ
1.How can I place an order for SSM3J112TU,LF through Aetrix?
Please submit a Request for Quotation (RFQ) for SSM3J112TU,LF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SSM3J112TU,LF reliable?
The price and inventory of SSM3J112TU,LF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SSM3J112TU,LF is usually 5 days.
3.What payment methods are accepted for SSM3J112TU,LF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SSM3J112TU,LF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SSM3J112TU,LF?
SSM3J112TU,LF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SSM3J112TU,LF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SSM3J112TU,LF?
For technical support, including SSM3J112TU,LF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SSM3J112TU,LF requirements.
6.How does Aetrix verify that SSM3J112TU,LF is sourced from the original manufacturer or authorized distributors?
All SSM3J112TU,LF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SSM3J112TU,LF meets industry standards.
7.What is the process for return or replacement of SSM3J112TU,LF?
All SSM3J112TU,LF units undergo pre-shipment inspection (PSI). If there is an issue with SSM3J112TU,LF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SSM3J112TU,LF part is unused and in its original packaging.
Return procedure for SSM3J112TU,LF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SSM3J112TU,LF Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

