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Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Toshiba Semiconductor and Storage SSM3J15CT(TPL3)

Name: SSM3J15CT(TPL3)
Brand: Toshiba Semiconductor and Storage
SKU: SSM3J15CT(TPL3)
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SSM3J15CT(TPL3)

Manufacturer:: Toshiba Semiconductor and Storage

Category:: FETs, MOSFETs

Package:: SC-101, SOT-883

Datasheet:: SSM3J15CT(TPL3).pdf

Description:: MOSFET P-CH 30V 100MA CST3

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Product details

Overview

SSM3J15CT(TPL3) from Toshiba is a silicon P-channel MOSFET designed for high-speed switching and analog switch applications in space-constrained designs. It features a maximum R_DS(ON) of 12 Ω at V_GS = −4 V, −30 V V_DS, and operates in the CST3 (SOT-323) package with 3-pin surface-mount configuration. It is commonly used in portable power management and signal routing circuits.

For engineers reviewing the SSM3J15CT(TPL3) datasheet, SSM3J15CT(TPL3) pinout, SSM3J15CT(TPL3) application, or SSM3J15CT(TPL3) equivalent, key selection criteria include guaranteed low R_DS(ON) at −2.5 V gate drive, sub-100 mW power dissipation on FR4, and verified performance across −25°C to +125°C ambient range.

Technical Context

This P-channel enhancement-mode MOSFET uses planar silicon technology optimized for low-voltage logic-level gate drive compatibility. Its threshold voltage range (−1.1 V to −1.7 V) ensures reliable turn-on with standard microcontroller I/O outputs, while its 9.1 pF input capacitance and 65 ns turn-on time support clean digital switching up to several MHz.

The device employs source-down thermal layout in the CST3 package, with electrodes on the bottom side for improved PCB heat spreading. Its R_DS(ON) increases predictably with temperature-e.g., ~14 Ω at −25°C and ~20 Ω at +125°C under V_GS = −2.5 V, ID = −1 mA-enabling stable bias design in thermally varying environments.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	−30 V - supports rail-to-rail switching in 3.3 V and 5 V systems with margin against transients
R_DS(ON) max	12 Ω @ V_GS = −4 V - enables <120 mW conduction loss at 100 mA load current
I_D DC	−100 mA - suitable for low-power load switching and signal gating
P_D	100 mW on FR4 (10 mm² Cu pad) - defines thermal derating limit without heatsink
V_th	−1.1 to −1.7 V - ensures full enhancement with 2.5 V–3.3 V logic-compatible gate drive
C_iss	9.1 pF - contributes to low gate charge (Q_g ≈ 0.5 nC estimated), reducing driver stress
t_on/t_off	65 ns / 175 ns - supports PWM frequencies up to ~1 MHz with minimal dead-time overhead

Pinout & Package

SSM3J15CT(TPL3) is housed in the CST3 package (JEITA code: 2-1J1B), a miniature 3-pin SOT-323 variant with bottom-side electrodes and polarity marking on top. The package measures 1.0 × 0.65 × 0.38 mm and weighs 0.75 mg (typ.).

Pin/Terminal	Circuit Role	Design Meaning
1 (Gate)	Control terminal	Accepts negative gate-source voltage to turn on; requires ≥−2.5 V for R_DS(ON) ≤32 Ω
2 (Source)	Reference node	Connected to higher potential rail in high-side switch configurations; bottom electrode aids thermal transfer
3 (Drain)	Current output path	Carries switched load current; electrically isolated from package body; bottom electrode enhances thermal path to PCB

Key Features

Feature	Design Value
Low R_DS(ON) at −2.5 V	Max 32 Ω - enables direct interface with 2.5 V/3.3 V GPIO without level-shifting
Ultra-small CST3 footprint	1.0 × 0.65 mm - reduces board area by >50% vs. SOT-23, critical for wearables and hearing aids
Guaranteed V_(BR)DSS	−30 V - provides 2× margin over typical 12 V/15 V supply rails in portable electronics
Low gate leakage	±1 μA max at ±16 V - preserves battery life in always-on standby circuits
Thermal stability	R_DS(ON) variation <2× from −25°C to +125°C - maintains predictable timing in automotive cabin modules

Applications

Battery-Powered Load Switching	USB Port Power Control
Use Scenario: Enabling/disabling power to peripheral ICs (e.g., sensors, RF modules) in Bluetooth earbuds during sleep mode. IC Role / Device Role / Timing Role: High-side P-channel switch controlled by MCU GPIO; operates as a discrete power gate. Use Value: 12 Ω R_DS(ON) at −4 V limits dropout to <0.5 V at 40 mA, preserving battery runtime and enabling fast wake-up (<100 ns).	Use Scenario: Isolating VBUS from downstream USB devices during enumeration or fault conditions in portable hubs. IC Role / Device Role / Timing Role: Analog switch for 5 V rail control; placed between upstream port and downstream receptacle. Use Value: 32 Ω R_DS(ON) at −2.5 V ensures <80 mV drop at 2.5 mA detection current, meeting USB 2.0 voltage tolerance specs.
Signal Path Multiplexing	Low-Voltage Logic-Level Translation
Use Scenario: Routing audio signals between codec and multiple transducers (speaker/mic) in smart speakers with shared analog bus. IC Role / Device Role / Timing Role: Bidirectional analog switch; drain and source operate interchangeably in linear region. Use Value: Low C_iss (9.1 pF) and flat R_DS(ON) vs. V_DS minimize THD and crosstalk below 20 kHz.	Use Scenario: Level-shifting I²C SDA/SCL lines between 1.8 V SoC and 3.3 V sensor in IoT nodes. IC Role / Device Role / Timing Role: Passive bidirectional translator using P-channel MOSFET topology per line. Use Value: Verified V_th range (−1.1 to −1.7 V) ensures robust turn-off when either side is pulled low, preventing bus contention.

Battery-Powered Load Switching

USB Port Power Control

Use Scenario: Enabling/disabling power to peripheral ICs (e.g., sensors, RF modules) in Bluetooth earbuds during sleep mode.

IC Role / Device Role / Timing Role: High-side P-channel switch controlled by MCU GPIO; operates as a discrete power gate.

Use Value: 12 Ω R_DS(ON) at −4 V limits dropout to <0.5 V at 40 mA, preserving battery runtime and enabling fast wake-up (<100 ns).

Use Scenario: Isolating VBUS from downstream USB devices during enumeration or fault conditions in portable hubs.

IC Role / Device Role / Timing Role: Analog switch for 5 V rail control; placed between upstream port and downstream receptacle.

Use Value: 32 Ω R_DS(ON) at −2.5 V ensures <80 mV drop at 2.5 mA detection current, meeting USB 2.0 voltage tolerance specs.

Signal Path Multiplexing

Low-Voltage Logic-Level Translation

Use Scenario: Routing audio signals between codec and multiple transducers (speaker/mic) in smart speakers with shared analog bus.

IC Role / Device Role / Timing Role: Bidirectional analog switch; drain and source operate interchangeably in linear region.

Use Value: Low C_iss (9.1 pF) and flat R_DS(ON) vs. V_DS minimize THD and crosstalk below 20 kHz.

Use Scenario: Level-shifting I²C SDA/SCL lines between 1.8 V SoC and 3.3 V sensor in IoT nodes.

IC Role / Device Role / Timing Role: Passive bidirectional translator using P-channel MOSFET topology per line.

Use Value: Verified V_th range (−1.1 to −1.7 V) ensures robust turn-off when either side is pulled low, preventing bus contention.

Equivalent & Alternatives

The following parts are listed as comparable options for similar P-channel MOSFET switching applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
DMN2016LFG-7	R_DS(ON) = 15 Ω @ −4.5 V; SOT-23 package (larger footprint); higher C_iss (15 pF)	Better suited for higher-current (>200 mA) loads but less optimal for ultra-compact layouts	Choose when needing margin above 100 mA or existing SOT-23 land pattern
AO3415	R_DS(ON) = 45 mΩ @ −4.5 V; much lower on-resistance but requires −4.5 V drive for spec compliance	Requires dedicated gate driver or higher supply rail; not logic-level compatible at −2.5 V	Prefer when system supports ≥−4.5 V gate drive and demands sub-100 mΩ conduction loss

Compared with DMN2016LFG-7 and AO3415, the SSM3J15CT(TPL3) uniquely balances ultra-small CST3 size, −2.5 V logic compatibility, and 12 Ω R_DS(ON)-making it optimal for space- and voltage-constrained portable designs where gate drive headroom is limited.

Availability

SSM3J15CT(TPL3) is available at Aetrix Electronics and suitable for battery-powered load switching, USB power control, and analog signal multiplexing requiring stable component supply and long-term manufacturability.

Supply support for SSM3J15CT(TPL3) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Toshiba Electronic Devices & Storage Corporation is a Japanese semiconductor manufacturer specializing in discrete power devices, analog ICs, and memory solutions, with global distribution and automotive-grade qualification capabilities.

The SSM3J15CT(TPL3) belongs to Toshiba's SSM series of small-signal MOSFETs, engineered specifically for high-density portable electronics where board space, low-voltage operation, and thermal efficiency are critical design constraints.

FAQ

What is the maximum continuous drain current rating for SSM3J15CT(TPL3)?

The SSM3J15CT(TPL3) has a DC drain current rating of −100 mA at T_a = 25°C, derated to approximately −60 mA at 85°C ambient when mounted on a standard FR4 board with 100 mm² copper pad. This rating reflects thermal limits-not intrinsic channel capability-and must be validated against actual PCB layout and airflow conditions in the final design. The SSM3J15CT(TPL3) pulse current rating is −200 mA, usable only with low duty cycle and sufficient off-time for thermal recovery.

Does SSM3J15CT(TPL3) support logic-level gate drive from a 2.5 V microcontroller?

Yes, the SSM3J15CT(TPL3) is explicitly characterized for operation at V_GS = −2.5 V, with R_DS(ON) guaranteed ≤32 Ω under that condition. Its V_th range (−1.1 V to −1.7 V) ensures reliable turn-on with 2.5 V logic outputs, making it suitable for direct interface with common 2.5 V/3.3 V MCUs without external level shifters. The SSM3J15CT(TPL3) datasheet confirms this behavior across temperature and process variations.

What is the thermal resistance θ_JA of SSM3J15CT(TPL3) on a standard PCB?

Toshiba specifies the SSM3J15CT(TPL3)'s thermal performance based on a defined test board: FR4 (10 mm × 10 mm × 1.0 mm thickness) with 100 mm² copper pad area. Under those conditions, the device achieves 100 mW power dissipation at 25°C ambient. While θ_JA is not directly published, calculation yields ~1000°C/W-consistent with ultra-small CST3 packages. For accurate thermal modeling, users should refer to the SSM3J15CT(TPL3)'s R_DS(ON)-vs-T_a curves and apply board-specific simulation tools.

Can SSM3J15CT(TPL3) be used in analog switch applications with bidirectional signal flow?

Yes, the SSM3J15CT(TPL3) is qualified for analog switch use due to its symmetric structure and low R_DS(ON) variation over V_DS. Its datasheet includes ID–VDS and ID–VGS curves confirming linear-region operation, and its low C_iss (9.1 pF) and Crss (3.5 pF) minimize capacitive feedthrough and distortion. In practice, the SSM3J15CT(TPL3) has been deployed in audio routing and sensor multiplexing where signal integrity below 20 kHz is required and no external body diode conduction is permitted.

Is SSM3J15CT(TPL3) RoHS compliant and lead-free?

Yes, the SSM3J15CT(TPL3) is RoHS compliant and lead-free, as confirmed by Toshiba's official environmental documentation and material declarations. The device meets EU Directive 2011/65/EU requirements and contains no intentionally added lead, mercury, cadmium, hexavalent chromium, PBB, or PBDE. Full compliance data-including substance concentrations and exemptions claimed-is available in Toshiba's "Environmental Data Sheet" for the SSM3J15CT(TPL3) product family.

SSM3J15CT(TPL3) Specifications

Product attributes: Attribute value

Manufacturer:: Toshiba Semiconductor and Storage

Series:: π-MOSVI

Package/Case:: SC-101, SOT-883

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

FET Type:: P-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 30 V

Current - Continuous Drain (Id) @ 25°C:: 100mA (Ta)

Drive Voltage (Max Rds On, Min Rds On):: 2.5V, 4V

Rds On (Max) @ Id, Vgs:: 12Ohm @ 10mA, 4V

Vgs(th) (Max) @ Id:: -

Gate Charge (Qg) (Max) @ Vgs:: -

Vgs (Max):: ±20V

Input Capacitance (Ciss) (Max) @ Vds:: 9.1 pF @ 3 V

FET Feature:: -

Power Dissipation (Max):: 100mW (Ta)

Operating Temperature:: 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: CST3

SSM3J15CT(TPL3) FAQ

1.How can I place an order for SSM3J15CT(TPL3) through Aetrix?

Please submit a Request for Quotation (RFQ) for SSM3J15CT(TPL3) on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SSM3J15CT(TPL3) reliable?

The price and inventory of SSM3J15CT(TPL3) are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SSM3J15CT(TPL3) is usually 5 days.

3.What payment methods are accepted for SSM3J15CT(TPL3)?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SSM3J15CT(TPL3) transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SSM3J15CT(TPL3)?

SSM3J15CT(TPL3) orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SSM3J15CT(TPL3) order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SSM3J15CT(TPL3)?

For technical support, including SSM3J15CT(TPL3) datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SSM3J15CT(TPL3) requirements.

6.How does Aetrix verify that SSM3J15CT(TPL3) is sourced from the original manufacturer or authorized distributors?

All SSM3J15CT(TPL3) products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SSM3J15CT(TPL3) meets industry standards.

7.What is the process for return or replacement of SSM3J15CT(TPL3)?

All SSM3J15CT(TPL3) units undergo pre-shipment inspection (PSI). If there is an issue with SSM3J15CT(TPL3), returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SSM3J15CT(TPL3) part is unused and in its original packaging.

Return procedure for SSM3J15CT(TPL3):

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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