Toshiba Semiconductor and Storage SSM3K15ACT(TPL3)

Overview

SSM3K15ACT(TPL3) from Toshiba is a silicon N-channel MOSFET in the U-MOS III process, designed for low-voltage load switching. It delivers R_DS(ON) = 3.6 Ω (max) at V_GS = 4 V and 6.0 Ω (max) at V_GS = 2.5 V, supports 30 V V_DSS, 100 mA continuous drain current, and operates in CST3 surface-mount package - ideal for space-constrained power management in portable electronics.

For engineers reviewing the SSM3K15ACT(TPL3) datasheet, SSM3K15ACT(TPL3) pinout, SSM3K15ACT(TPL3) application, or SSM3K15ACT(TPL3) equivalent, key selection criteria include verified 2.5 V logic-level gate drive capability, thermal performance on FR4 (100 mW @ T_a = 25°C), channel temperature limit of 150°C, and confirmed suitability for discrete load switch implementations requiring fast turn-on/turn-off times (t_on = 5.5 ns, t_off = 35 ns).

Technical Context

This N-channel enhancement-mode MOSFET uses Toshiba's U-MOS III trench-gate structure to achieve low R_DS(ON) with minimal gate charge. Its V_th range (0.8–1.5 V) enables reliable switching with 2.5 V microcontroller outputs, while |Y_fs| = 35 mS ensures strong transconductance for stable current control under pulsed loads.

The device exhibits C_iss = 13.5 pF, C_oss = 8.0 pF, and C_rss = 6.5 pF at V_DS = 3 V, supporting high-speed switching in low-power DC-DC and battery-protection circuits. Absolute maximum ratings are defined for FR4 board mounting (10 mm × 10 mm × 1.0 mm, 100 mm² Cu pad), with derating required above 25°C ambient.

Key Specifications

Pinout & Package

SSM3K15ACT(TPL3) is housed in the CST3 (Chip-Scale Transistor) package - a 1.2 mm × 1.2 mm × 0.5 mm ultra-small surface-mount outline with bottom-side electrodes and top-side polarity marking. The package features three terminals: Gate (G), Source (S), and Drain (D), with no exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel load switch applications.

Compared with DMN2004LK-7 and AO3414, the SSM3K15ACT(TPL3) offers tighter R_DS(ON) tolerance at 2.5 V, smaller CST3 footprint, and lower input capacitance - making it optimal for miniaturized, low-voltage IoT and wearable designs where gate drive voltage margin and board area are critical.

Availability

SSM3K15ACT(TPL3) is available at Aetrix Electronics and suitable for USB power switching, smartphone battery protection, wearable sensor gating, and IoT LED control applications requiring stable component supply and consistent parametric performance across production lots.

Supply support for SSM3K15ACT(TPL3) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Toshiba Electronic Devices & Storage Corporation designs and manufactures discrete semiconductors, power devices, and logic ICs with emphasis on efficiency, miniaturization, and reliability for consumer, industrial, and automotive markets.

The SSM3K15ACT(TPL3) belongs to Toshiba's U-MOS III N-channel MOSFET family, engineered specifically for ultra-compact, low-voltage load switching in battery-powered portable electronics where gate drive simplicity and thermal efficiency are essential.

FAQ

What is the maximum continuous drain current for SSM3K15ACT(TPL3) under standard PCB conditions?

The SSM3K15ACT(TPL3) supports 100 mA continuous drain current (I_D) when mounted on a standard FR4 board (10 mm × 10 mm × 1.0 mm, 100 mm² Cu pad) at T_a = 25°C. Derating applies above this temperature - for example, ~60 mA at 85°C ambient - per the PD–T_a curve in the official Toshiba datasheet for SSM3K15ACT(TPL3).

Does SSM3K15ACT(TPL3) support true 2.5 V logic-level gate drive?

Yes, the SSM3K15ACT(TPL3) is fully specified for 2.5 V operation: R_DS(ON) is guaranteed ≤6.0 Ω (max) at V_GS = 2.5 V and I_D = 10 mA (pulse test). Its V_th range (0.8–1.5 V) provides sufficient margin for reliable turn-on with 2.5 V GPIOs, as confirmed in Toshiba's electrical characteristics table for SSM3K15ACT(TPL3).

What is the thermal resistance from channel to ambient for SSM3K15ACT(TPL3)?

Toshiba does not publish R_th(ch–a) as a fixed value for SSM3K15ACT(TPL3); instead, it specifies 100 mW power dissipation on a defined FR4 test board. Using P_D = (T_ch − T_a) / R_th(ch–a), the effective R_th(ch–a) is ~1400°C/W under those exact conditions - but actual values depend heavily on PCB copper area and layer stack-up, as noted in the thermal design precautions for SSM3K15ACT(TPL3).

Can SSM3K15ACT(TPL3) be used in avalanche mode?

No - the SSM3K15ACT(TPL3) datasheet explicitly warns: "Do not use this device under avalanche mode. It may cause the device to break down." The device is not rated for unclamped inductive switching or repetitive avalanche energy; external clamping (e.g., TVS diode or RC snubber) is required if driving inductive loads with SSM3K15ACT(TPL3).

What is the package type and pin configuration of SSM3K15ACT(TPL3)?

The SSM3K15ACT(TPL3) uses the CST3 (Chip-Scale Transistor) package: 1.2 mm × 1.2 mm × 0.5 mm, with bottom-side electrodes and top-side polarity mark. Pin 1 is Gate, Pin 2 is Source, Pin 3 is Drain - confirmed by Toshiba's mechanical drawing and marking diagram for SSM3K15ACT(TPL3).