Toshiba Semiconductor and Storage SSM3K16CT(TPL3)

Overview

SSM3K16CT(TPL3) from Toshiba is a silicon N-channel MOSFET designed for high-speed and analog switching in low-voltage, space-constrained circuits. It delivers R_DS(ON) = 3.0 Ω (max) at V_GS = 4 V, supports V_DS = 20 V and I_D = 100 mA DC, and uses the ultra-compact CST3 (SC-108) package with 0.75 mg typical weight - ideal for portable power management and signal routing in wearables and IoT edge nodes.

For engineers reviewing the SSM3K16CT(TPL3) datasheet, SSM3K16CT(TPL3) pinout, SSM3K16CT(TPL3) application, or SSM3K16CT(TPL3) equivalent, key selection criteria include verified low-threshold operation (V_th = 0.6–1.1 V), sub-10 pF input capacitance, guaranteed turn-on/turn-off times (t_on = 70 ns, t_off = 125 ns), and thermal derating behavior on FR4 boards.

Technical Context

This discrete N-channel enhancement-mode MOSFET operates as a single-pole, single-throw (SPST) voltage-controlled switch. Its gate threshold voltage range (0.6–1.1 V) enables reliable turn-on from 1.8 V and 2.5 V logic rails, while its low C_iss (9.3 pF typ.) and C_rss (4.5 pF typ.) minimize Miller-induced switching delays and EMI in fast-switching paths.

The device employs planar silicon process technology with bottom-side source/drain electrodes and top-side gate marking. Thermal performance is specified for mounting on a 10 mm × 10 mm × 1.0 mm FR4 board with 100 mm² copper pad, delivering P_D = 100 mW at T_a = 25°C and derating to zero at T_a = 150°C.

Key Specifications

Pinout & Package

SSM3K16CT(TPL3) uses the CST3 (JEITA SC-108, also known as SC-70-3) surface-mount package: 1.2 mm × 0.8 mm × 0.5 mm body, 0.75 mg typical weight, with exposed drain electrode on the bottom side and polarity mark on top. Pin 1 = Gate, Pin 2 = Source, Pin 3 = Drain.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel small-signal MOSFET applications.

Compared with DMN2004K-7 and AO3400, SSM3K16CT(TPL3) offers the smallest footprint and lowest V_th among the three, making it uniquely suited for 1.8 V–2.5 V logic-driven analog switching where board area and gate drive voltage are constrained.

Availability

SSM3K16CT(TPL3) is available at Aetrix Electronics and suitable for portable audio signal routing, wearable sensor power gating, and USB-C port multiplexing requiring stable component supply and long-term lifecycle support.

Supply support for SSM3K16CT(TPL3) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Toshiba Electronic Devices & Storage Corporation designs and manufactures discrete semiconductors, power devices, and logic ICs with emphasis on reliability, miniaturization, and energy efficiency for consumer, industrial, and automotive markets.

The SSM3K16CT(TPL3) belongs to Toshiba's SSM series of ultra-small-signal MOSFETs, engineered specifically for high-density analog and digital switching in battery-powered portable electronics where size, low-voltage drive, and thermal efficiency are critical.

FAQ

What is the maximum continuous drain current rating for SSM3K16CT(TPL3)?

The SSM3K16CT(TPL3) has a DC drain current rating of 100 mA at T_a = 25°C, derated linearly to zero at 150°C ambient. This rating assumes mounting on a 10 mm × 10 mm FR4 board with 100 mm² copper pad. At 85°C ambient, the usable I_D drops to approximately 60 mA, and actual design margins should account for PCB layout and airflow.

Does SSM3K16CT(TPL3) support 1.8 V logic-level gate drive?

Yes, SSM3K16CT(TPL3) supports 1.8 V logic-level gate drive due to its guaranteed V_th range of 0.6–1.1 V. At V_GS = 1.8 V, R_DS(ON) remains ≤15 Ω (max) with I_D = 1 mA, enabling functional switching in low-power enable/control applications - though full performance (R_DS(ON) ≤3.0 Ω) requires ≥4 V gate voltage.

What is the thermal resistance (R_θJA) of SSM3K16CT(TPL3) on standard FR4?

The SSM3K16CT(TPL3) does not specify R_θJA directly, but its P_D = 100 mW at T_a = 25°C and zero dissipation at T_a = 150°C imply an effective R_θJA ≈ 1250°C/W under the defined test condition (10 mm × 10 mm FR4, 100 mm² Cu pad). Layout optimization with additional thermal vias can improve this by up to 40%.

Is SSM3K16CT(TPL3) RoHS compliant and lead-free?

Yes, SSM3K16CT(TPL3) is RoHS compliant and lead-free, conforming to EU Directive 2011/65/EU and Toshiba's environmental specifications. The device uses matte tin plating on terminals and halogen-free molding compound. Full compliance documentation, including substance declarations and test reports, is available upon request from Aetrix Electronics.

How does the bottom-side drain electrode affect PCB layout for SSM3K16CT(TPL3)?

The bottom-side drain electrode of SSM3K16CT(TPL3) must be soldered to a dedicated PCB copper pour for optimal thermal and electrical performance. A minimum 1 mm² exposed drain pad with ≥4 thermal vias (0.3 mm diameter) to inner ground/power planes is recommended. Misalignment or insufficient solder paste volume risks voiding and elevated junction temperature during 100 mA operation.