Toshiba Semiconductor and Storage SSM5N15FU,LF
- Part No.:
- SSM5N15FU,LF
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- FETs, MOSFETs
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
SSM5N15FU,LF.pdf
- Description:
- MOSFET N-CH 30V 100MA USV
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SSM5N15FU,LF from Toshiba Electronic Devices & Storage Corporation is a dual-channel silicon N-channel MOSFET in a compact SOT-363 (SC-88) package, rated for 30 V VDS, 100 mA continuous drain current, and featuring RDS(ON) = 4.0 Ω max at VGS = 4 V. It serves as a low-power analog or high-speed switching device in signal routing and load control circuits.
For engineers reviewing the SSM5N15FU,LF datasheet, SSM5N15FU,LF pinout, SSM5N15FU,LF application, or SSM5N15FU,LF equivalent, key selection criteria include its dual-N-channel topology, low gate threshold voltage (0.8–1.5 V), sub-8 pF input capacitance, 50 ns turn-on time, and suitability for space-constrained portable electronics requiring low-voltage logic-level drive.
Technical Context
The SSM5N15FU,LF integrates two independent N-channel enhancement-mode MOSFETs in a single 6-pin SOT-363 package with common-source configuration capability. Its low Vth enables direct interface with 2.5 V and 3.3 V logic families, while RDS(ON) performance across VGS = 2.5 V (7.0 Ω max) and 4.0 V (4.0 Ω max) supports flexible biasing in battery-powered systems.
Designed for analog switching and high-speed digital switching, it exhibits Ciss = 7.8 pF typ., Crss = 3.6 pF typ., and fast switching times (ton = 50 ns max, toff = 180 ns max at VDD = 5 V), enabling clean signal integrity in multiplexing and power gating applications up to several MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS Rating | 30 V - Supports operation in 3.3 V, 5 V, and 12 V rail systems with margin against transients. |
| RDS(ON) @ VGS = 4 V | 4.0 Ω max - Enables ≤40 mW conduction loss at 100 mA, suitable for low-power analog switches. |
| Vth Range | 0.8–1.5 V - Ensures reliable turn-on with standard LVCMOS/LVTTL outputs without level-shifting. |
| Ciss | 7.8 pF typ. - Minimizes capacitive loading on driving logic, preserving signal edge rates in multiplexers. |
| ton/toff | 50 ns / 180 ns max - Supports switching frequencies up to ~1 MHz in non-resonant digital control paths. |
| PD (Total) | 200 mW - Limits thermal rise in SOT-363 package; requires derating above 25°C ambient per datasheet curve. |
Pinout & Package
SSM5N15FU,LF uses the JEITA-registered 6-pin SOT-363 (SC-88) surface-mount package, measuring 2.0 × 1.25 × 0.9 mm (typ.), with 6 mg mass and RoHS-compliant finish. Pin numbering follows top-view marking convention with "D P" indicator.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Source Q1 | Common source terminal for first MOSFET channel; internally tied to Pin 2 in typical dual-SO configuration. |
| 2 | Drain Q1 | Output node for Q1; routed to external load or signal path; shares thermal pad with Q2 drain. |
| 3 | Gate Q1 | Control input for Q1; accepts logic-level signals; ESD-protected per handling precautions. |
| 4 | Gate Q2 | Independent control input for second MOSFET; electrically isolated from Q1 gate. |
| 5 | Drain Q2 | Output node for Q2; symmetrical to Pin 2; supports dual independent switching paths. |
| 6 | Source Q2 | Source terminal for Q2; not internally connected to Pin 1 - discrete dual-channel layout. |
Key Features
| Feature | Design Value |
|---|---|
| Dual N-channel topology | Two independent MOSFETs in one SOT-363 footprint - reduces PCB area by ~40% vs. discrete SOT-23 pair. |
| Low VGS(th) | 0.8–1.5 V range - eliminates need for gate boosters when driven by 1.8 V/2.5 V microcontrollers. |
| Low input capacitance | Ciss = 7.8 pF typ. - minimizes propagation delay and driver loading in high-frequency analog switches. |
| Guaranteed RDS(ON) | 7.0 Ω max at VGS = 2.5 V - ensures robust conduction under low-voltage battery conditions (e.g., 2.7–3.0 V). |
Applications
| USB Data Line Switching | Low-Voltage Sensor Multiplexing |
|---|---|
Use Scenario: Routing USB 2.0 D+/D− signals between host and peripheral ports in portable docking stations. IC Role / Device Role / Timing Role: Dual-channel analog switch controlling bidirectional 480 Mbps differential data paths with minimal insertion loss. Use Value: RDS(ON) < 4 Ω and Ciss < 8 pF preserve signal integrity up to 200 MHz; SOT-363 footprint fits tight spacing near USB connectors. | Use Scenario: Selecting between multiple temperature or pressure sensors sharing a single ADC input in wearable health monitors. IC Role / Device Role / Timing Role: Low-leakage analog multiplexer enabling sequential sensor readout without cross-talk or offset drift. Use Value: IDSS ≤ 1 μA and RDS(ON) flatness over VGS ensure <0.1% gain error; dual channels reduce BOM count vs. discrete FETs. |
| Logic-Level Power Gating | Portable Audio Signal Routing |
Use Scenario: Enabling/disabling power to BLE radio modules or display backlights in coin-cell–powered IoT nodes. IC Role / Device Role / Timing Role: Low-quiescent-current load switch controlled directly by MCU GPIO pins. Use Value: Vth ≤ 1.5 V allows full enhancement at 1.8 V IO, while 200 mW PD rating supports 100 mA loads without heatsinking. | Use Scenario: Muting/unmuting left/right audio channels or selecting between microphone inputs in Bluetooth earbuds. IC Role / Device Role / Timing Role: Low-distortion analog switch handling line-level AC-coupled audio signals (±0.5 V peak). Use Value: Low RDS(ON) and matched channel characteristics minimize THD+N; 150°C Tch rating accommodates sealed enclosure thermal profiles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-N-channel MOSFET switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DMN2004LSD-13 | Higher VDS (20 V), lower RDS(ON) (2.5 Ω @ 4.5 V), SOT-26 package | Requires ≥4.5 V gate drive for optimal RDS(ON); less suitable for 2.5 V systems | Prefer when higher current (>150 mA) and tighter RDS(ON) tolerance are needed, and 4.5 V logic is available. |
| FDMA1023PZ | Single-channel P-channel, −20 V VDS, 2.8 Ω RDS(ON) @ −4.5 V, WDFN-6 package | Inverts control logic; suited for high-side load switching rather than low-side/analog routing | Select only for high-side power gating where active-low enable and polarity inversion are acceptable. |
Compared with DMN2004LSD-13 and FDMA1023PZ, the SSM5N15FU,LF uniquely balances dual-N-channel functionality, 2.5 V logic compatibility, and ultra-small SOT-363 size-making it optimal for space-limited, low-voltage analog/digital switching where gate drive headroom is constrained.
Availability
SSM5N15FU,LF is available at Aetrix Electronics and suitable for USB switching, sensor multiplexing, logic-level power gating, and portable audio routing requiring stable component supply and long-term industrial availability.
Supply support for SSM5N15FU,LF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs and manufactures discrete semiconductors, power devices, and logic ICs with emphasis on reliability, miniaturization, and energy efficiency for consumer, industrial, and automotive markets.
The SSM5N15FU,LF belongs to Toshiba's SSM series of small-signal MOSFETs, engineered specifically for high-density portable electronics requiring dual-channel, low-voltage-switching capability in sub-2 mm² footprints.
FAQ
What is the maximum continuous drain current rating for the SSM5N15FU,LF?
The SSM5N15FU,LF is rated for 100 mA DC drain current per channel at Ta = 25°C. This rating assumes proper PCB thermal relief and derating per the datasheet's PD vs. Ta curve; at 70°C ambient, usable current drops to approximately 60 mA to maintain safe channel temperature.
Does the SSM5N15FU,LF support 1.8 V logic-level gate drive?
The SSM5N15FU,LF has a gate threshold voltage range of 0.8–1.5 V, making it functional with 1.8 V logic. However, RDS(ON) is not guaranteed below VGS = 2.5 V; at 1.8 V, conduction resistance rises significantly-designers should verify voltage drop and power dissipation in actual operating conditions for the SSM5N15FU,LF.
Is the SSM5N15FU,LF pin-compatible with other Toshiba SSM-series dual MOSFETs?
No-the SSM5N15FU,LF uses a unique 6-pin SOT-363 pinout (1:S1, 2:D1, 3:G1, 4:G2, 5:D2, 6:S2) that differs from SSM3K327R or SSM3J327R. Pin mapping must be verified per each device's datasheet; no generic pin-compatibility exists across the SSM family for the SSM5N15FU,LF.
What is the thermal resistance θJA for the SSM5N15FU,LF in standard FR-4 PCB layout?
The datasheet does not specify θJA for the SSM5N15FU,LF. Based on JEDEC-standard SOT-363 thermal characterization and typical 2-layer FR-4 layouts with 1 cm² copper pour, θJA is estimated at ~350°C/W. For thermal design, use the absolute maximum Tch = 150°C and the provided PD vs. Ta derating curve to size traces accordingly for the SSM5N15FU,LF.
Are there any special handling requirements for the SSM5N15FU,LF during assembly?
Yes-the SSM5N15FU,LF is ESD-sensitive (HBM Class 1B per datasheet handling precautions). Operators must use anti-static workstations, wrist straps, and conductive foam trays; reflow profiles must comply with JEDEC J-STD-020 moisture sensitivity level (MSL) 1, and PCB layout should avoid floating gate traces to prevent unintended turn-on of the SSM5N15FU,LF.
SSM5N15FU,LF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- π-MOSVI
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 100mA (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 2.5V, 4V
- Rds On (Max) @ Id, Vgs:
- 4Ohm @ 10mA, 4V
- Vgs(th) (Max) @ Id:
- -
- Gate Charge (Qg) (Max) @ Vgs:
- -
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 7.8 pF @ 3 V
- FET Feature:
- -
- Power Dissipation (Max):
- 200mW (Ta)
- Operating Temperature:
- 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-SSOP
SSM5N15FU,LF FAQ
1.How can I place an order for SSM5N15FU,LF through Aetrix?
Please submit a Request for Quotation (RFQ) for SSM5N15FU,LF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SSM5N15FU,LF reliable?
The price and inventory of SSM5N15FU,LF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SSM5N15FU,LF is usually 5 days.
3.What payment methods are accepted for SSM5N15FU,LF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SSM5N15FU,LF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SSM5N15FU,LF?
SSM5N15FU,LF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SSM5N15FU,LF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SSM5N15FU,LF?
For technical support, including SSM5N15FU,LF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SSM5N15FU,LF requirements.
6.How does Aetrix verify that SSM5N15FU,LF is sourced from the original manufacturer or authorized distributors?
All SSM5N15FU,LF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SSM5N15FU,LF meets industry standards.
7.What is the process for return or replacement of SSM5N15FU,LF?
All SSM5N15FU,LF units undergo pre-shipment inspection (PSI). If there is an issue with SSM5N15FU,LF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SSM5N15FU,LF part is unused and in its original packaging.
Return procedure for SSM5N15FU,LF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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