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Toshiba Semiconductor and Storage SSM6P40TU,LF
- Part No.:
- SSM6P40TU,LF
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- FET, MOSFET Arrays
- Package:
- 6-SMD, Flat Leads
- Datasheet:
-
SSM6P40TU,LF.pdf
- Description:
- MOSFET 2P-CH 30V 1.4A UF6
- Quantity:
- Payment:
- Shipping:
Inventory:14,001
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Product details
Overview
SSM6P40TU,LF from Toshiba is a dual P-channel MOSFET in a 6-pin UDFN package, designed for power management and high-speed switching applications. It features low on-resistance (226 mΩ max at VGS = –10 V), ±20 V gate-source voltage rating, and –30 V drain-source breakdown voltage. The device supports 4.0 V logic-level drive and operates with a maximum channel temperature of 150 °C.
For engineers reviewing the SSM6P40TU,LF datasheet, SSM6P40TU,LF pinout, SSM6P40TU,LF application, or SSM6P40TU,LF equivalent, this page delivers verified electrical characteristics, validated dual-MOSFET terminal mapping, thermal derating guidance, and real-world switching performance data under pulsed and DC conditions.
Technical Context
The SSM6P40TU,LF integrates two identical enhancement-mode P-channel MOSFETs in a common-source configuration with shared thermal path. Each channel exhibits gate threshold voltage between –0.8 V and –2.0 V, enabling reliable turn-on with 4 V drive while maintaining robust off-state isolation up to –30 V.
Its dynamic performance includes 12 ns turn-on time and 8.5 ns turn-off time (VDD = –15 V, RG = 10 Ω), supported by low input capacitance (Ciss = 120 pF) and minimal reverse transfer capacitance (Crss = 21 pF), making it suitable for high-frequency load switching in compact DC-DC and battery-protection circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDSS | –30 V - Maximum blocking voltage before avalanche conduction in power switch mode |
| RDS(on) | 226 mΩ (max @ VGS = –10 V) - Enables <1.5 W conduction loss at 1.4 A DC current |
| ID (DC) | –1.4 A - Continuous drain current capability with FR4 board mounting (645 mm² copper pad) |
| Vth | –0.8 to –2.0 V - Ensures full enhancement-mode operation with standard 3.3 V/5 V logic-compatible gate drive |
| Ciss | 120 pF - Low input capacitance reduces gate drive power and speeds up switching transitions |
| ton/toff | 12 ns / 8.5 ns - Supports >30 MHz switching frequency in pulse-width modulated load control |
| PD | 500 mW - Total dissipation limit on standard FR4 PCB; derates linearly above 25 °C ambient |
Pinout & Package
SSM6P40TU,LF uses a 6-pin ultra-thin UDFN package (2.0 × 2.1 × 0.3 mm, JEITA code 2-2T1B), optimized for space-constrained portable and battery-powered designs. Thermal resistance is minimized via exposed drain pad connected to internal Q1 and Q2 drains.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Source 1 | Source terminal of first P-channel MOSFET; tied to local ground reference for independent channel control |
| 2 | Gate 1 | Control input for Q1; requires negative gate bias relative to source to conduct |
| 3 | Drain 2 | Output node of second MOSFET; internally bonded to exposed thermal pad for heat dissipation |
| 4 | Source 2 | Source terminal of second P-channel MOSFET; electrically isolated from Source 1 unless externally connected |
| 5 | Gate 2 | Independent control input for Q2; enables dual-load switching without cross-talk |
| 6 | Drain 1 | Output node of first MOSFET; shares thermal pad with Drain 2 for symmetrical power handling |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level compatible drive | Operates fully enhanced at VGS = –4 V - eliminates need for gate boosters in 3.3 V systems |
| Dual independent channels | Two matched P-MOSFETs in single package - reduces board area vs. discrete dual-SOT-363 solutions |
| Low gate charge | Qg = 2.9 nC - minimizes driver IC loading and switching energy loss |
| Thermally optimized layout | Exposed drain pad connects both drains - improves thermal conductivity to PCB copper for sustained 1.4 A operation |
| ESD-protected structure | ±1 μA gate leakage at ±16 V - meets JEDEC JS-001 Class 2 (2 kV HBM) requirements per handling precautions |
Applications
| Battery Protection Circuit | USB Port Power Switch |
|---|---|
Use Scenario: Dual-MOSFET back-to-back configuration prevents reverse current flow during battery charging/discharging cycles in Li-ion packs. IC Role / Device Role / Timing Role: P-channel MOSFET pair acting as bidirectional blocking switch with integrated thermal monitoring. Use Value: RDS(on) ≤ 403 mΩ at –4 V ensures <600 mW total conduction loss at 1.4 A, extending battery runtime and reducing thermal stress. | Use Scenario: Hot-swap enable/disable of USB 2.0 downstream ports in portable hubs and docking stations. IC Role / Device Role / Timing Role: Dual load switch controlling VBUS power delivery with independent enable control per port. Use Value: 12 ns ton enables clean power sequencing within USB specification rise-time limits (<100 ms), preventing enumeration failures. |
| LED Backlight Dimming | Power-Rail Sequencing |
Use Scenario: PWM-controlled current sink for white LED strings in small-form-factor displays. IC Role / Device Role / Timing Role: High-side P-MOSFET switch modulating cathode-side current with fast edge control. Use Value: Crss = 21 pF minimizes Miller effect, sustaining >10 kHz dimming frequency without gate oscillation or shoot-through risk. | Use Scenario: Controlled ramp-up of multiple supply rails (e.g., core, I/O, analog) in FPGA or SoC power domains. IC Role / Device Role / Timing Role: Independent high-side switches enabling staggered turn-on timing via separate gate signals. Use Value: Matched Vth (–0.8 to –2.0 V) across both channels ensures consistent turn-on delay, eliminating rail collapse during sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual P-channel MOSFET switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DMG6968UVT-7 | Single-channel, 2 mm × 2 mm TSOP-6; RDS(on) = 28 mΩ @ –4.5 V (lower on-resistance but higher VGS(th) = –1.5 V min) | Requires two devices for dual-switch function; lacks integrated dual topology | Preferred when lower conduction loss justifies added component count and layout area |
| AO6401 | Dual P-MOSFET in TSOP-6; RDS(on) = 130 mΩ @ –4.5 V but rated only to –20 V VDSS | Not suitable for –30 V bus protection; limited to 3.3 V/5 V logic systems with lower voltage rails | Select only if system VDS remains ≤ –20 V and tighter RDS(on) is critical |
Compared with DMG6968UVT-7 and AO6401, the SSM6P40TU,LF uniquely combines –30 V rating, 4 V logic compatibility, and monolithic dual-channel integration in a 2.0 × 2.1 mm footprint-enabling single-component solutions for space- and voltage-critical battery management and USB power delivery.
Availability
SSM6P40TU,LF is available at Aetrix Electronics and suitable for battery protection circuits, USB power switches, LED backlight dimming, and power-rail sequencing requiring stable component supply and long-term industrial availability.
Supply support for SSM6P40TU,LF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation is a global semiconductor manufacturer specializing in power semiconductors, logic ICs, and memory solutions, with emphasis on energy efficiency and reliability.
The SSM6P40TU,LF belongs to Toshiba's SSM series of small-signal and power MOSFETs, engineered specifically for compact, high-efficiency load switching in portable electronics and battery-powered systems.
FAQ
What is the maximum continuous drain current rating for the SSM6P40TU,LF?
The SSM6P40TU,LF has a DC drain current rating of –1.4 A per channel when mounted on a standard FR4 board (25.4 mm × 25.4 mm × 1.6 mm with 645 mm² copper pad). This rating assumes Ta = 25 °C and accounts for thermal limitations; derating is required above ambient temperatures of 25 °C per the PD–Ta curve in the datasheet. The SSM6P40TU,LF must not exceed its absolute maximum channel temperature of 150 °C under any operating condition.
Does the SSM6P40TU,LF support 3.3 V logic-level gate drive?
Yes, the SSM6P40TU,LF is fully specified for 4.0 V drive and exhibits RDS(on) = 403 mΩ (max) at VGS = –4 V, making it compatible with 3.3 V microcontroller outputs when referenced to a negative gate bias scheme. Its gate threshold voltage range of –0.8 V to –2.0 V ensures strong enhancement-mode behavior at 3.3 V logic swing. The SSM6P40TU,LF does not require level-shifting circuitry in typical 3.3 V system designs.
How are the two MOSFETs configured internally in the SSM6P40TU,LF?
The SSM6P40TU,LF contains two independent P-channel MOSFETs (Q1 and Q2) in a common-source topology with no internal connection between sources or gates. Pin 1 is Source 1, Pin 4 is Source 2, Pin 2 is Gate 1, Pin 5 is Gate 2, Pin 6 is Drain 1, and Pin 3 is Drain 2. Both drains connect to the same exposed thermal pad. The SSM6P40TU,LF allows fully independent control of each channel for dual-load switching or back-to-back configurations.
What is the thermal resistance (RθJA) of the SSM6P40TU,LF on a standard FR4 board?
The SSM6P40TU,LF has a junction-to-ambient thermal resistance of approximately 250 °C/W when mounted on a 25.4 mm × 25.4 mm × 1.6 mm FR4 board with 645 mm² copper pad, derived from its 500 mW power dissipation rating and 125 °C allowable temperature rise (150 °C Tch – 25 °C Ta). Transient thermal impedance data shows rθ drops to ~100 °C/W for 10 ms pulses, confirming suitability for short-duration peak loads. The SSM6P40TU,LF thermal performance is optimized for compact layouts with direct thermal coupling to PCB copper.
Can the SSM6P40TU,LF be used in automotive applications?
The SSM6P40TU,LF is not qualified for automotive use per AEC-Q101 and is explicitly excluded from unintended use categories including automotive systems per Toshiba's restrictions notice. It lacks extended temperature grade (–40 to 125 °C), automotive-specific qualification testing, and failure rate documentation. For automotive-grade dual P-MOSFETs, alternative parts with AEC-Q101 certification must be selected. The SSM6P40TU,LF is intended for commercial and industrial portable electronics only.
SSM6P40TU,LF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- -
- Package/Case:
- 6-SMD, Flat Leads
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- MOSFET (Metal Oxide)
- Configuration:
- 2 P-Channel (Dual)
- FET Feature:
- Logic Level Gate, 4V Drive
- Drain to Source Voltage (Vdss):
- 30V
- Current - Continuous Drain (Id) @ 25°C:
- 1.4A (Ta)
- Rds On (Max) @ Id, Vgs:
- 226mOhm @ 1A, 10V
- Vgs(th) (Max) @ Id:
- 2V @ 1mA
- Gate Charge (Qg) (Max) @ Vgs:
- 2.9nC @ 10V
- Input Capacitance (Ciss) (Max) @ Vds:
- 120pF @ 15V
- Power - Max:
- 500mW (Ta)
- Operating Temperature:
- 150°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- UF6
SSM6P40TU,LF FAQ
1.How can I place an order for SSM6P40TU,LF through Aetrix?
Please submit a Request for Quotation (RFQ) for SSM6P40TU,LF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SSM6P40TU,LF reliable?
The price and inventory of SSM6P40TU,LF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SSM6P40TU,LF is usually 5 days.
3.What payment methods are accepted for SSM6P40TU,LF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SSM6P40TU,LF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SSM6P40TU,LF?
SSM6P40TU,LF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SSM6P40TU,LF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SSM6P40TU,LF?
For technical support, including SSM6P40TU,LF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SSM6P40TU,LF requirements.
6.How does Aetrix verify that SSM6P40TU,LF is sourced from the original manufacturer or authorized distributors?
All SSM6P40TU,LF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SSM6P40TU,LF meets industry standards.
7.What is the process for return or replacement of SSM6P40TU,LF?
All SSM6P40TU,LF units undergo pre-shipment inspection (PSI). If there is an issue with SSM6P40TU,LF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SSM6P40TU,LF part is unused and in its original packaging.
Return procedure for SSM6P40TU,LF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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