STMicroelectronics STB28NM50N
- Part No.:
- STB28NM50N
- Manufacturer:
- STMicroelectronics
- Category:
- FETs, MOSFETs
- Package:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Datasheet:
-
STB28NM50N.pdf
- Description:
- MOSFET N-CH 500V 21A D2PAK
- Quantity:
- Payment:

- Shipping:

Inventory:185
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Product details
Overview
STB28NM50N from STMicroelectronics is an N-channel 500 V, 135 mΩ typ. (158 mΩ max.), 21 A MDmesh™ II Power MOSFET in D²PAK (TO-263) package, designed for high-efficiency hard-switched and resonant-mode SMPS topologies including PFC stages and LLC converters. It features 100% avalanche tested ruggedness, low gate charge (50 nC), and low input capacitance (1735 pF), enabling fast switching with reduced driver loss.
For engineers reviewing the STB28NM50N datasheet, STB28NM50N pinout, STB28NM50N application, or STB28NM50N equivalent, key selection criteria include its 500 V VDS, 158 mΩ RDS(on) at 10 VGS, 50 nC total gate charge, 150 W power dissipation at TC = 25 °C, and D²PAK thermal resistance of 0.83 °C/W (junction-to-case).
Technical Context
This device implements ST's second-generation MDmesh™ vertical superjunction architecture with strip layout, delivering ultra-low RDS(on) × Qg figure-of-merit (8.4 Ω·nC) for high-frequency operation. Its 150 °C maximum junction temperature and 2.5 kV insulation withstand voltage support robust isolation in industrial and telecom power supplies.
The integrated body diode exhibits 326 ns reverse recovery time (TJ = 25 °C) and 5 µC Qrr, optimized for ZVS/ZCS soft-switching. Gate threshold voltage is tightly specified at 2–4 V, ensuring stable turn-on under wide VGS margin and compatible with standard 10 V gate drivers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 500 V - Withstands DC bus voltages up to 400 V in 380–400 VAC PFC applications with safety margin. |
| RDS(on) max | 158 mΩ at VGS = 10 V, ID = 10.5 A - Enables <1.7 W conduction loss at 21 A continuous current (TC = 25 °C). |
| Qg | 50 nC - Reduces gate drive power and enables use of low-power drivers in high-frequency (>100 kHz) designs. |
| Ciss | 1735 pF - Low input capacitance minimizes Miller effect and improves dv/dt immunity in fast-switching circuits. |
| PTOT | 150 W at TC = 25 °C - Supports high-power density when mounted on heatsink with low thermal resistance interface. |
| RthJC | 0.83 °C/W - Enables efficient heat transfer from die to heatsink; critical for thermal management in enclosed enclosures. |
| EAS | 300 mJ - Confirmed single-pulse avalanche energy allows reliable operation during transient overvoltage events without external snubbers. |
Pinout & Package
D²PAK (TO-263) package with exposed drain tab for thermal and electrical connection; surface-mount footprint optimized for high-current PCB layouts and automated assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Tab (Drain) | Power Drain terminal | Electrically and thermally connected to internal drain; must be soldered to large copper pour or heatsink for thermal performance. |
| Pin 1 (Gate) | Control input | High-impedance MOS gate requiring low-inductance routing and local 100 nF bypass capacitor near source. |
| Pin 2 (Source) | Reference node | Return path for load current and gate drive loop; must be low-inductance connection to minimize switching noise. |
| Pin 3 (Source) | Redundant source connection | Dual-source pins reduce source inductance and improve current sharing in high-di/dt applications. |
Key Features
| Feature | Design Value |
|---|---|
| 100% avalanche tested | Guarantees robustness against unclamped inductive switching stress without derating or external protection. |
| Low Qg / Ciss | 50 nC total gate charge and 1735 pF input capacitance enable >300 kHz operation with minimal driver loss. |
| MDmesh™ II architecture | Vertical superjunction structure achieves 135 mΩ typ. RDS(on) at 500 V, reducing conduction loss by ~25% vs. planar alternatives. |
| Low Rg | 2.7 Ω intrinsic gate resistance supports clean turn-on/turn-off waveforms and reduces gate ringing risk. |
| High dv/dt immunity | Rated for 15 V/ns peak diode recovery dv/dt, preventing false turn-on during hard commutation of inductive loads. |
Applications
| Industrial AC-DC Power Supplies | Telecom Rectifier Modules |
|---|---|
|
Use Scenario: 3.3 kW active clamp forward or phase-shifted full-bridge converter operating from 380 VAC input. IC Role / Device Role / Timing Role: Primary-side high-side switch handling 21 A RMS current at 100–200 kHz switching frequency. Use Value: 158 mΩ RDS(on) and 50 nC Qg reduce combined conduction + switching losses to <3.2 W, enabling >95% efficiency at full load. |
Use Scenario: 48 V output, 1200 W telecom rectifier with dual-phase interleaved PFC front-end. IC Role / Device Role / Timing Role: Boost switch in each PFC channel, conducting 18 A peak current with 500 V blocking capability. Use Value: 300 mJ EAS and 15 V/ns dv/dt rating eliminate need for clamping circuits during line surges or startup transients. |
| Solar Microinverters | Server PSU Main Switch |
|
Use Scenario: 300 W microinverter with transformerless H5 topology feeding 230 VAC grid. IC Role / Device Role / Timing Role: High-voltage bridge leg switch sustaining 500 V DC link and switching at 40–60 kHz. Use Value: Dual-source pins and 0.83 °C/W RthJC allow direct mounting to aluminum baseplate, maintaining TJ < 125 °C at 92% efficiency. |
Use Scenario: 1.5 kW server power supply using asymmetric half-bridge with synchronous rectification. IC Role / Device Role / Timing Role: High-side main switch in primary-side LLC resonant converter stage. Use Value: 1735 pF Ciss and 4.3 pF Crss minimize Miller-induced shoot-through risk during zero-voltage switching transitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage power switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STP28NM50N | Same die, TO-220 package; RthJC = 0.83 °C/W but higher RthJA (50 °C/W); no exposed drain tab. | Preferred for prototyping or low-volume through-hole assembly; less suitable for high-power density SMT designs. | Select when mechanical mounting flexibility or socket-based testing is required; avoid in space-constrained SMT layouts. |
| IPP60R190C7 | 650 V, 190 mΩ, 21 A, CoolMOS™ C7; lower Qg (37 nC) but higher RDS(on); not 100% avalanche tested. | Better suited for 400–450 VDC bus systems where higher VDS margin is needed; requires external avalanche protection. | Choose for higher bus voltage headroom or lower gate drive loss; verify avalanche capability via external circuit design. |
Compared with STP28NM50N, STB28NM50N offers superior thermal performance in SMT layouts due to D²PAK's lower RthJA (30 °C/W on FR-4) and integrated heatsink interface; versus IPP60R190C7, it delivers proven avalanche ruggedness at lower cost for 500 V-class designs without sacrificing switching speed.
Availability
STB28NM50N is available at Aetrix Electronics and suitable for industrial AC-DC power supplies, telecom rectifier modules, and solar microinverters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for STB28NM50N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and power management applications.
The STB28NM50N belongs to ST's MDmesh™ II Power MOSFET product line, engineered specifically for high-efficiency, high-voltage switched-mode power supplies where low RDS(on) × Qg and avalanche ruggedness are critical.
FAQ
What is the maximum continuous drain current for STB28NM50N at 100 °C case temperature?
The maximum continuous drain current is 13 A at TC = 100 °C, limited by junction temperature (TJ ≤ 150 °C). This value is confirmed in Table 1 of DS6813 Rev 3 and reflects thermal derating due to reduced heat transfer at elevated case temperatures.
Does STB28NM50N require a gate resistor for safe operation?
Yes - a gate resistor (typically 4.7 Ω) is recommended to control dV/dt and suppress oscillation, as validated in the datasheet's Figure 17 test circuit. The device's 2.7 Ω intrinsic gate resistance alone is insufficient to dampen ringing in high-di/dt applications.
Can STB28NM50N replace STP28NM50N in an existing TO-220 PCB layout?
No - STB28NM50N uses D²PAK (TO-263) packaging with different pad layout, thermal pad requirement, and pin assignment (G-S-S-D vs. G-D-S). Direct replacement requires PCB redesign to accommodate the surface-mount footprint and exposed drain tab.
Is the body diode of STB28NM50N suitable for synchronous rectification?
No - the body diode has 326 ns reverse recovery time and 5 µC Qrr, making it unsuitable for synchronous rectification. It is optimized for freewheeling in hard-switched topologies, not high-frequency bidirectional conduction.
STB28NM50N Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- MDmesh™ II
- Package/Case:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 500 V
- Current - Continuous Drain (Id) @ 25°C:
- 21A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 158mOhm @ 10.5A, 10V
- Vgs(th) (Max) @ Id:
- 4V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 50 nC @ 10 V
- Vgs (Max):
- ±25V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1735 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 150W (Tc)
- Operating Temperature:
- 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- D2PAK
STB28NM50N FAQ
1.How can I place an order for STB28NM50N through Aetrix?
Please submit a Request for Quotation (RFQ) for STB28NM50N on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STB28NM50N reliable?
The price and inventory of STB28NM50N are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STB28NM50N is usually 5 days.
3.What payment methods are accepted for STB28NM50N?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STB28NM50N transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STB28NM50N?
STB28NM50N orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STB28NM50N order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STB28NM50N?
For technical support, including STB28NM50N datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STB28NM50N requirements.
6.How does Aetrix verify that STB28NM50N is sourced from the original manufacturer or authorized distributors?
All STB28NM50N products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STB28NM50N meets industry standards.
7.What is the process for return or replacement of STB28NM50N?
All STB28NM50N units undergo pre-shipment inspection (PSI). If there is an issue with STB28NM50N, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STB28NM50N part is unused and in its original packaging.
Return procedure for STB28NM50N:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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