STMicroelectronics STD3NM60N

Overview

STD3NM60N from STMicroelectronics is an N-channel 600 V, 1.6 Ω (typ), 3.3 A MDmesh™ II Power MOSFET in DPAK (TO-252) package. It delivers low gate charge (9.5 nC), low input capacitance (188 pF), and 100% avalanche tested ruggedness for high-efficiency offline SMPS, PFC stages, and industrial motor drives.

For engineers reviewing the STD3NM60N datasheet, STD3NM60N pinout, STD3NM60N application, or STD3NM60N equivalent, key selection criteria include its 600 V V(BR)DSS rating, RDS(on) stability over temperature, fast switching (tr = 9.5 ns), integrated source-drain diode with trr = 200 ns at 25 °C, and thermal resistance junction-to-case of 2.5 °C/W.

Technical Context

This device employs ST's second-generation MDmesh™ vertical strip architecture to minimize conduction and switching losses simultaneously. Its optimized cell layout achieves low RDS(on) × Qg figure-of-merit (1.6 Ω × 9.5 nC ≈ 15.2 Ω·nC), enabling high-frequency operation in hard-switched topologies up to 100 kHz.

The integrated body diode supports synchronous rectification and inductive load commutation, with characterized reverse recovery parameters (Qrr = 910 nC, IRRM = 9.1 A) at 100 A/µs di/dt and 60 V VDD. Safe operating area (SOA) is defined up to 10 ms pulse width at Tc = 25 °C.

Key Specifications

Pinout & Package

DPAK (TO-252) package: surface-mount, single-die, 3-terminal configuration with exposed drain tab for thermal and electrical connection. Tab is electrically connected to Drain (Pin 2). Standard JEDEC MO-236 outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage power switching applications.

Compared with STP3NK60Z and FQP3N60C, STD3NM60N offers superior RDS(on) × Qg trade-off, surface-mount DPAK packaging for compact designs, and guaranteed avalanche capability-making it preferred for space-constrained, high-reliability 600 V SMPS where thermal and switching efficiency are prioritized.

Availability

STD3NM60N is available at Aetrix Electronics and suitable for AC-DC adapters, industrial PFC modules, LED driver power stages, and isolated DC-DC converters requiring stable component supply and long-term production continuity.

Supply support for STD3NM60N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for industrial, automotive, and consumer markets.

STD3NM60N belongs to ST's MDmesh™ II high-voltage power MOSFET product line, engineered specifically for high-efficiency, high-frequency offline power conversion in space-constrained applications demanding low conduction and switching losses.

FAQ

What is the maximum continuous drain current at 100 °C case temperature?

The STD3NM60N supports 2.5 A continuous drain current at TC = 100 °C, as specified in Table 2 of the datasheet. This derating reflects thermal limitations of the DPAK package and ensures safe operation within its 2.5 °C/W junction-to-case thermal resistance and 150 °C maximum junction temperature.

Does STD3NM60N have built-in gate protection?

No, STD3NM60N does not integrate gate Zener protection. Its absolute maximum gate-source voltage is ±25 V, and gate leakage is limited to ±100 nA at ±25 V. External gate resistors and TVS clamps are recommended in noisy environments or when driving from high-impedance sources to prevent ESD damage or overvoltage stress.

Can STD3NM60N replace STD3NK60Z in existing designs?

Direct replacement is not recommended without validation. STD3NK60Z has higher RDS(on) (2.2 Ω), different gate threshold (2–4 V vs. 2–3 V typ), and no specified avalanche rating. While pin-compatible in DPAK, differences in Qg (9.5 nC vs. 12 nC), Ciss (188 pF vs. 230 pF), and SOA require re-evaluation of gate drive strength, snubber design, and transient stress margins.

What is the typical reverse recovery time of the body diode?

The typical reverse recovery time (trr) of the integrated source-drain diode is 200 ns at TJ = 25 °C, ISD = 3.3 A, di/dt = 100 A/µs, and VDD = 60 V (Table 8). At TJ = 150 °C, trr increases to 236 ns, reflecting temperature-dependent minority carrier lifetime in the epitaxial layer.