STMicroelectronics STD6N80K5

Overview

STD6N80K5 from STMicroelectronics is an N-channel 800 V, 1.6 Ω (max) MDmesh K5 Power MOSFET in DPAK package, delivering 4.5 A continuous drain current at 25 °C and ultra-low 13 nC total gate charge. It features 100% avalanche testing, Zener-protected gate, and is optimized for high-voltage switching in offline SMPS and PFC stages.

For engineers reviewing the STD6N80K5 datasheet, STD6N80K5 pinout, STD6N80K5 application, or STD6N80K5 equivalent, key selection criteria include R_DS(on) × area efficiency, dv/dt ruggedness (4.5 V/ns), single-pulse avalanche energy (85 mJ), and thermal resistance (1.47 °C/W junction-to-case).

Technical Context

This device implements ST's MDmesh K5 vertical superjunction architecture to achieve industry-leading figure of merit (R_DS(on) × Q_g = 20.8 Ω·nC) and low output capacitance (C_oss = 25 pF typ.). Its gate threshold voltage (3–5 V) ensures robust TTL/CMOS drive compatibility while maintaining noise immunity.

The integrated source-drain diode exhibits 280 ns reverse recovery time (T_J = 25 °C) and 2.2 µC Q_rr, enabling hard-switched operation with minimized commutation loss. The 1.47 °C/W R_thJC supports high-power density layouts on minimal copper area.

Key Specifications

Pinout & Package

DPAK (TO-252) package with exposed drain tab for thermal and electrical connection; thermally enhanced layout compatible with FR-4 PCBs using ≥1 in² 2 oz copper.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage power switching applications.

Compared with STP6N80K5, STD6N80K5 offers superior PCB thermal performance and lower profile; versus IPP60R190C7, it trades higher R_DS(on) for guaranteed 800 V operation and better dv/dt immunity in noisy grid-connected equipment.

Availability

STD6N80K5 is available at Aetrix Electronics and suitable for industrial AC-DC adapters, server PSU primary switches, and PFC boost stages requiring stable component supply across multi-year production cycles.

Supply support for STD6N80K5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, with manufacturing, R&D, and sales operations across Asia, Europe, and the Americas.

This device belongs to the MDmesh K5 high-voltage Power MOSFET product line, engineered specifically for high-efficiency, high-power-density offline switching applications including telecom rectifiers, industrial PSUs, and lighting drivers.

FAQ

What is the maximum continuous drain current at 100 °C case temperature?

The STD6N80K5 supports 2.8 A continuous drain current at T_C = 100 °C, as specified in Table 1 of DS9676 Rev 5. This derating reflects thermal limitations of the DPAK package and must be applied in thermal simulations when ambient exceeds 50 °C or airflow is restricted.

Does this MOSFET include integrated gate protection?

Yes - the STD6N80K5 integrates a bidirectional Zener diode between gate and source, rated for ±20 V clamp voltage. This eliminates the need for external gate protection components in most applications, reducing BOM count and board area.

Can STD6N80K5 replace older MDmesh K3 devices in existing designs?

Yes, with validation: it shares identical pinout and voltage rating with STD6N80K3, but delivers 30% lower R_DS(on) and 25% lower Q_g. Layout changes are not required, though gate drive strength and snubber tuning may benefit from the improved switching characteristics.

What is the recommended PCB footprint for thermal performance?

Per Figure 21 in DS9676 Rev 5, use a minimum 1 in² (645 mm²) 2 oz copper pour connected directly to the exposed drain tab. Include ≥6 thermal vias (0.3 mm diameter, 0.6 mm pitch) under the tab to inner ground/power planes for optimal R_thJC utilization.