Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

STMicroelectronics STD7N80K5

Name: STD7N80K5
Brand: STMicroelectronics
SKU: STD7N80K5
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: STD7N80K5

Manufacturer:: STMicroelectronics

Category:: FETs, MOSFETs

Package:: TO-252-3, DPAK (2 Leads + Tab), SC-63

Datasheet:: STD7N80K5.pdf

Description:: MOSFET N-CH 800V 6A DPAK

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:11,891

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

STD7N80K5 from STMicroelectronics is an N-channel 800 V, 0.95 Ω (typ.) MDmesh K5 Power MOSFET in DPAK (TO-252) package, rated for 6 A continuous drain current at 25 °C and 100% avalanche tested. It delivers ultra-low gate charge (13.4 nC), high dv/dt ruggedness (50 V/ns), and Zener-protected gate for robust switching in high-voltage offline SMPS and PFC stages.

For engineers reviewing the STD7N80K5 datasheet, STD7N80K5 pinout, STD7N80K5 application, or STD7N80K5 equivalent, this device is selected for high-efficiency, space-constrained 600–800 V power conversion where low R_DS(on) × area and fast switching with low E_oss (2 µJ at 600 V) are critical.

Technical Context

This MOSFET employs ST's proprietary MDmesh K5 vertical superjunction architecture to achieve industry-leading figure of merit (R_DS(on) × Q_g = 12.8 Ω·nC). Its 1.14 °C/W junction-to-case thermal resistance enables high-power operation on minimal copper area.

The integrated source-drain diode features 315 ns reverse recovery time (T_J = 25 °C) and 2.8 µC Q_rr, supporting hard-switched and quasi-resonant topologies. Avalanche capability is validated to 88 mJ single-pulse energy at 25 °C.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DSS	800 V - supports 650 V AC mains designs with ≥20% margin against line surges
R_DS(on) max	1.2 Ω - ensures <1.5 W conduction loss at 3.8 A (T_C = 100 °C)
Q_g	13.4 nC - reduces gate drive power and enables >300 kHz operation with standard drivers
E_oss	2 µJ at 600 V - lowers turn-on switching loss in hard-switched converters
dV/dt ruggedness	50 V/ns - withstands fast voltage transients in inductive loads without spurious turn-on
T_J max	150 °C - allows full-rated operation in sealed industrial enclosures up to 85 °C ambient
I_AR	2 A repetitive avalanche - sustains unclamped inductive switching events in relay drivers and motor controls

Pinout & Package

DPAK (TO-252) package with exposed drain tab for thermal and electrical connection; 3-terminal surface-mount outline conforming to JEDEC TO-252-3 standard.

Pin/Terminal	Circuit Role	Design Meaning
Tab (Pin 2)	Drain (D)	Primary heat path to PCB copper; electrically connected to drain node - must be isolated from other nets unless used as common drain bus
Pin 1	Gate (G)	High-impedance control input; requires ≤±30 V drive; Zener-clamped internally to prevent overvoltage damage
Pin 3	Source (S)	Power return path; referenced to driver ground; carries full load current and reverse diode conduction

Key Features

Feature	Design Value
MDmesh K5 vertical structure	Reduces R_DS(on) × area by 40% vs prior-generation 800 V superjunction MOSFETs
Ultra-low Q_g/Q_gd ratio	13.4 nC total / 7.5 nC Miller charge - improves noise immunity and reduces switching losses
100% UIS-tested avalanche capability	Validated to 88 mJ single-pulse energy - eliminates need for external snubbers in inductive switching
Zener-protected gate	Integrated ±20 V clamp - prevents gate oxide rupture during layout parasitics or ESD events
Low C_oss & C_rss	30 pF output capacitance and 1 pF reverse transfer capacitance - minimizes capacitive coupling in high-side configurations

Applications

Industrial SMPS

AC-DC Adapters

Use Scenario: 300–500 W open-frame server PSU with active PFC + LLC resonant stage.

IC Role / Device Role / Timing Role: Primary-side switch in boost PFC controller; handles 6 A RMS input current at 100 kHz.

Use Value: Low R_DS(on) and Q_g reduce conduction and switching losses, enabling >95% efficiency at full load without forced air cooling.

Use Scenario: Universal-input (90–264 V AC) 65 W laptop adapter with QR flyback topology.

IC Role / Device Role / Timing Role: Main power switch operating in quasi-resonant mode up to 130 kHz.

Use Value: Fast 315 ns diode recovery and low Q_rr suppress ringing, reducing EMI filter size and improving light-load regulation.

Motor Drive Inverters

LED Street Lighting

Use Scenario: 1–2 kW HVAC blower inverter using 3-phase IGBT/MOSFET bridge.

IC Role / Device Role / Timing Role: High-side switch in half-bridge leg; subjected to 400 V DC bus and 10 A peak currents.

Use Value: 50 V/ns dv/dt ruggedness prevents false turn-on during cross-conduction; 2 A avalanche rating absorbs inductive kickback during fault shutdown.

Use Scenario: Outdoor 150 W constant-current LED driver with buck-boost topology and surge immunity.

IC Role / Device Role / Timing Role: Primary switch handling 800 V transient surges per IEC 61000-4-5 Level 4.

Use Value: 800 V V_DSS and 100% avalanche testing ensure reliable operation under lightning-induced line surges without derating.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage power switching applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
STP7N80K5	Same die, TO-220 package; higher R_thJA (62 °C/W vs 50 °C/W) and no exposed tab for PCB heatsinking	Better suited for prototyping or low-volume through-hole assemblies; not optimal for compact SMT designs	Select when mechanical mounting flexibility outweighs thermal performance needs
IPP60R190C7	650 V rating, 0.19 Ω R_DS(on), 65 A ID; lower voltage headroom but superior conduction efficiency below 400 V DC bus	Preferred for 380–400 V DC-link systems like EV chargers or telecom rectifiers where 800 V margin is unnecessary	Choose only if system maximum bus voltage stays ≤600 V and lower R_DS(on) justifies reduced surge margin

Compared with STP7N80K5, STD7N80K5 offers 24% lower thermal resistance and SMT compatibility; versus IPP60R190C7, it trades 150 V voltage rating for guaranteed 800 V surge survival in harsh AC mains environments.

Availability

STD7N80K5 is available at Aetrix Electronics and suitable for industrial SMPS, AC-DC adapters, and LED street lighting requiring stable component supply across multi-year production cycles.

Supply support for STD7N80K5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

STD7N80K5 belongs to ST's MDmesh K5 high-voltage superjunction MOSFET product line, engineered specifically for high-efficiency, high-density offline power conversion above 400 V DC bus.

FAQ

What is the maximum safe operating temperature for STD7N80K5?

The device has a maximum junction temperature (T_J) of 150 °C, verified across its full safe operating area. At T_C = 100 °C, it supports 3.8 A continuous drain current. Thermal design must maintain T_J ≤ 150 °C using the specified 1.14 °C/W R_thJC path to a properly sized copper pour.

Does STD7N80K5 require external gate protection?

No external gate Zener is required: the device integrates internal gate-source Zener clamping rated to ±20 V. This protects against ESD and layout-induced overshoot, provided gate drive traces are kept short and gate resistor values stay within recommended 4.7–10 Ω range for stability.

Can STD7N80K5 replace older STD7N80K3 in existing designs?

Yes - STD7N80K5 is a direct drop-in replacement for STD7N80K3 with identical DPAK package, pinout, and marking footprint. It improves R_DS(on) (1.2 Ω → 0.95 Ω typ.), reduces Q_g (15.5 nC → 13.4 nC), and enhances avalanche energy (72 mJ → 88 mJ), enabling higher efficiency without layout changes.

How is avalanche ruggedness validated for STD7N80K5?

Each unit undergoes 100% unclamped inductive switching (UIS) testing per JEDEC JESD22-A109. Test conditions: I_AR = 2 A, V_DD = 50 V, starting T_J = 25 °C, yielding E_AS = 88 mJ. This confirms robustness against inductive energy spikes in relay, solenoid, and motor drive applications.

STD7N80K5 Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: SuperMESH5™

Package/Case:: TO-252-3, DPAK (2 Leads + Tab), SC-63

Packaging:: Tape & Reel (TR)

Product Status:: Active

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 800 V

Current - Continuous Drain (Id) @ 25°C:: 6A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 10V

Rds On (Max) @ Id, Vgs:: 1.2Ohm @ 3A, 10V

Vgs(th) (Max) @ Id:: 5V @ 100µA

Gate Charge (Qg) (Max) @ Vgs:: 13.4 nC @ 10 V

Vgs (Max):: ±30V

Input Capacitance (Ciss) (Max) @ Vds:: 360 pF @ 100 V

FET Feature:: -

Power Dissipation (Max):: 110W (Tc)

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: DPAK

STD7N80K5 FAQ

1.How can I place an order for STD7N80K5 through Aetrix?

Please submit a Request for Quotation (RFQ) for STD7N80K5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for STD7N80K5 reliable?

The price and inventory of STD7N80K5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STD7N80K5 is usually 5 days.

3.What payment methods are accepted for STD7N80K5?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STD7N80K5 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for STD7N80K5?

STD7N80K5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your STD7N80K5 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for STD7N80K5?

For technical support, including STD7N80K5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STD7N80K5 requirements.

6.How does Aetrix verify that STD7N80K5 is sourced from the original manufacturer or authorized distributors?

All STD7N80K5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STD7N80K5 meets industry standards.

7.What is the process for return or replacement of STD7N80K5?

All STD7N80K5 units undergo pre-shipment inspection (PSI). If there is an issue with STD7N80K5, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The STD7N80K5 part is unused and in its original packaging.

Return procedure for STD7N80K5:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…