STMicroelectronics STH200N10WF7-2
- Part No.:
- STH200N10WF7-2
- Manufacturer:
- STMicroelectronics
- Category:
- FETs, MOSFETs
- Package:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Datasheet:
-
STH200N10WF7-2.pdf
- Description:
- N-CHANNEL 100 V, 4.8 MOHM TYP.,
- Quantity:
- Payment:

- Shipping:

Inventory:796
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Product details
Overview
STH200N10WF7-2 from STMicroelectronics is an N-channel 100 V, 3.2 mΩ typ. (4.0 mΩ max.), 180 A continuous, 340 W power MOSFET in H²PAK-2 package, utilizing STripFET F7 trench technology to deliver best-in-class SOA and linear-mode robustness for high-current switching and clamping applications including hot-swap and electronic fuse circuits.
For engineers reviewing the STH200N10WF7-2 datasheet, STH200N10WF7-2 pinout, STH200N10WF7-2 application, or STH200N10WF7-2 equivalent, key selection criteria include RDS(on) at 10 V gate drive, 720 A pulsed current capability, 840 mJ single-pulse avalanche energy, SOA curve compliance at 10 ms–dc, and thermal resistance of 0.44 °C/W junction-to-case.
Technical Context
This MOSFET employs an enhanced trench gate structure optimized for wide safe operating area (SOA) in linear mode while maintaining low conduction loss-enabling reliable operation under high VDS/ID stress conditions such as in-rush limiting and electronic fuse shutdown. Its 175 °C maximum junction temperature and -55 °C minimum storage temperature support industrial and automotive-grade thermal cycling.
The device features a source-drain diode with 1.2 V forward voltage at 180 A and fast recovery (trr = 85 ns, Qrr = 125 nC), enabling efficient synchronous rectification or freewheeling in high-frequency load-switch topologies without external diode supplementation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 100 V - Maximum drain-source blocking voltage; supports 48 V bus systems with ≥2× safety margin against transients. |
| RDS(on) max | 4.0 mΩ at VGS = 10 V, ID = 90 A - Enables <1.8 W conduction loss at 150 A, critical for thermally constrained hot-swap modules. |
| ID cont @ TC = 25 °C | 180 A - High continuous current rating allows single-device implementation in 100–200 A load switch designs. |
| EAS | 840 mJ - Single-pulse avalanche energy at VDD = 25 V; ensures ruggedness during unclamped inductive turn-off events. |
| RthJC | 0.44 °C/W - Low junction-to-case thermal resistance enables direct heatsink mounting with minimal thermal interface resistance. |
| trr | 85 ns - Reverse recovery time at ISD = 180 A, di/dt = 100 A/µs; reduces switching loss and EMI in high-dV/dt load-switch transitions. |
Pinout & Package
H²PAK-2 is a surface-mount, isolated-tab power package with copper clip construction, optimized for high-current PCB mounting and thermal transfer via the exposed drain tab. It features three terminals: Drain (Tab), Gate (Pin 1), Source (Pins 2 & 3).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D (Tab) | Drain | Exposed copper tab electrically connected to drain; primary thermal path to heatsink; must be isolated from other layers per layout guidelines. |
| G (Pin 1) | Gate | Control input requiring ≤10 V drive; total gate charge Qg = 93 nC mandates low-impedance driver for <500 ns switching times. |
| S (Pins 2 & 3) | Source | Common return path for load current; dual-pin configuration lowers parasitic inductance and improves current sharing in high-di/dt operation. |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced SOA capability | DC-rated SOA up to 100 V × 1.8 A, 10 ms up to 100 V × 18 A - enables stable linear-mode operation for precision current limiting without thermal runaway. |
| High surge current rating | IDM = 720 A (pulsed) - supports >4× rated current for short-duration in-rush events in server PSUs and battery protection circuits. |
| Low RDS(on) × Qg figure-of-merit | 3.2 mΩ × 93 nC = 298 mΩ·nC - balances conduction and switching losses for high-efficiency 100 kHz–500 kHz load switching. |
| Robust avalanche performance | EAS = 840 mJ - exceeds JEDEC JESD24-11 requirements for repetitive unclamped inductive switching in motor drivers and DC-DC controllers. |
Applications
| Hot-Swap Controllers | Electronic Fuse Circuits |
|---|---|
Use Scenario: Insertion of line cards into live backplanes with 48 V or 54 V supply rails. IC Role / Device Role / Timing Role: Main power switch controlling upstream bus connection; operates in linear mode during soft-start and fault current limiting. Use Value: 175 °C TJ rating and wide SOA allow sustained 10–100 ms current limiting at 100+ A without thermal shutdown or latch-up. |
Use Scenario: Overcurrent protection for 12–48 V distribution networks in telecom and industrial PLCs. IC Role / Device Role / Timing Role: Primary current-sensing switch; triggered by external comparator or digital controller to interrupt fault current within microseconds. Use Value: 720 A pulsed current rating and 840 mJ avalanche energy ensure survival during short-circuit events before mechanical breakers act. |
| High-Current Load Switches | In-Rush Current Limiters |
Use Scenario: Power sequencing and isolation of FPGA, ASIC, or GPU power domains in AI accelerators and servers. IC Role / Device Role / Timing Role: High-side load switch controlled by PMIC or microcontroller GPIO; handles steady-state currents up to 180 A. Use Value: 4.0 mΩ RDS(on) limits conduction loss to <1.3 W at 180 A, reducing heatsink size and improving system efficiency. |
Use Scenario: Controlled ramp-up of capacitive loads (e.g., bulk capacitance >10,000 µF) in power supplies and battery chargers. IC Role / Device Role / Timing Role: Linear-mode current limiter during startup; gate voltage slew rate controlled to limit dI/dt to <100 A/ms. Use Value: Stable SOA down to 100 µs pulse width enables precise in-rush control without oscillation or thermal instability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel high-current power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IXTH180N10L2 | RDS(on) = 4.2 mΩ max, Qg = 105 nC, TO-247 package, RthJC = 0.35 °C/W | Higher thermal efficiency but larger footprint; requires through-hole assembly and taller heatsink clearance. | Preferred where board space permits and lower thermal resistance is prioritized over surface-mount compatibility. |
| IPB180N10N3 G | RDS(on) = 3.8 mΩ max, Qg = 112 nC, PG-H2PAK-2 package, RthJC = 0.42 °C/W, AEC-Q101 qualified | Automotive-qualified variant with tighter parametric spread; identical footprint but higher gate charge increases drive complexity. | Select when functional safety compliance (ISO 26262) or extended temperature validation (-40 to 175 °C) is mandatory. |
Compared with IXTH180N10L2 and IPB180N10N3 G, STH200N10WF7-2 offers the lowest RDS(on) × Qg product (298 vs 441 and 426 mΩ·nC), making it optimal for high-frequency, high-current load switching where both conduction and switching losses must be minimized simultaneously.
Availability
STH200N10WF7-2 is available at Aetrix Electronics and suitable for hot-swap controllers, electronic fuse circuits, and high-current load switches requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for industrial and telecom infrastructure programs.
Supply support for STH200N10WF7-2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for smart driving, power management, microcontrollers, sensors, and analog ICs across industrial, automotive, and consumer markets.
This device belongs to ST's STripFET F7 high-power MOSFET product line, engineered specifically for high-current, high-reliability linear and switching applications demanding wide SOA, low on-resistance, and robust avalanche performance in compact surface-mount packages.
FAQ
What is the maximum gate-source voltage rating for STH200N10WF7-2?
The absolute maximum VGS is ±20 V, as specified in Table 1 of DS11828 Rev 4. Operation beyond this range risks permanent gate oxide damage. Recommended gate drive is 10 V for full enhancement, with 12 V acceptable if transient overshoot is limited to <15 ns and peak amplitude stays below 18 V.
Can STH200N10WF7-2 be used in avalanche mode for energy clamping?
Yes - it is fully characterized for single-pulse avalanche with EAS = 840 mJ at TJ = 25 °C, VDD = 25 V, and IAV = 65 A. Repetitive avalanche is not guaranteed; design must ensure junction temperature remains ≤175 °C and pulse duty cycle is limited per Figure 1 SOA curve.
Is the H²PAK-2 package lead-free and RoHS compliant?
Yes - the device carries ECOPACK2 qualification, meeting RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006. The package uses matte tin plating on leads and lead-free solder-compatible terminations, with halogen-free molding compound per IEC 61249-2-21.
What is the recommended PCB footprint for thermal performance?
Per Figure 19 in DS11828 Rev 4, the recommended footprint uses a 10 mm × 10 mm exposed copper pad for the drain tab, connected to internal ground/power planes via ≥8 thermal vias (0.3 mm diameter, 0.6 mm pitch). Minimum copper thickness is 2 oz (70 µm) on outer layers to sustain 340 W dissipation at TC = 25 °C.
STH200N10WF7-2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- TO-263-3, D2PAK (2 Leads + Tab), TO-263AB
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 100 V
- Current - Continuous Drain (Id) @ 25°C:
- 180A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 4mOhm @ 90A, 10V
- Vgs(th) (Max) @ Id:
- 4.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 93 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 4430 pF @ 25 V
- FET Feature:
- -
- Power Dissipation (Max):
- 340W (Tc)
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- H2PAK-2
STH200N10WF7-2 FAQ
1.How can I place an order for STH200N10WF7-2 through Aetrix?
Please submit a Request for Quotation (RFQ) for STH200N10WF7-2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STH200N10WF7-2 reliable?
The price and inventory of STH200N10WF7-2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STH200N10WF7-2 is usually 5 days.
3.What payment methods are accepted for STH200N10WF7-2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STH200N10WF7-2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STH200N10WF7-2?
STH200N10WF7-2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STH200N10WF7-2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STH200N10WF7-2?
For technical support, including STH200N10WF7-2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STH200N10WF7-2 requirements.
6.How does Aetrix verify that STH200N10WF7-2 is sourced from the original manufacturer or authorized distributors?
All STH200N10WF7-2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STH200N10WF7-2 meets industry standards.
7.What is the process for return or replacement of STH200N10WF7-2?
All STH200N10WF7-2 units undergo pre-shipment inspection (PSI). If there is an issue with STH200N10WF7-2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STH200N10WF7-2 part is unused and in its original packaging.
Return procedure for STH200N10WF7-2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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