STMicroelectronics STL130N8F7

Overview

STL130N8F7 from STMicroelectronics is an N-channel Power MOSFET in PowerFLAT 5x6 package, rated for 80 V V_DS, 3.6 mΩ R_DS(on) max at 10 V V_GS, 120 A continuous drain current (T_C = 25 °C), and 135 W total power dissipation. It employs STripFET F7 trench technology for high-efficiency switching in DC-DC converters and motor drives.

For engineers reviewing the STL130N8F7 datasheet, STL130N8F7 pinout, STL130N8F7 application, or STL130N8F7 equivalent, key selection criteria include its low R_DS(on), high avalanche energy (515 mJ), Crss/Ciss ratio for EMI immunity, and thermal resistance (R_thj-case = 1.1 °C/W) in compact surface-mount form.

Technical Context

This MOSFET uses enhanced trench gate structure to minimize conduction loss and switching losses simultaneously: R_DS(on) is 3.0 mΩ typ. at 10 V V_GS, while C_iss = 6340 pF and C_rss/C_iss ≈ 1.7% ensures robust EMI performance. Gate charge is optimized with Q_g = 96 nC, Q_gd = 26 nC, enabling fast turn-on/turn-off (t_d(on) = 26 ns, t_f = 44 ns).

It operates across -55 to 175 °C junction temperature range and supports unclamped inductive switching with single-pulse avalanche capability up to 515 mJ (V_DD = 50 V, I_D = 18.5 A). Thermal design is enabled by validated R_thj-case = 1.1 °C/W and R_thj-pcb = 31.3 °C/W on FR-4 (1 in², 2 oz Cu).

Key Specifications

Pinout & Package

STL130N8F7 uses PowerFLAT 5x6 type C package (JEDEC MO-263AC), a 5 mm × 6 mm surface-mount outline with exposed drain pad for thermal and electrical performance. The package features 8 terminals arranged in two rows, with drain connected to pins 5–8, gate to pin 4, and source to pins 1–3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel 80 V power MOSFET applications.

Compared with IPP036N08N and NTMFS5C673NL, STL130N8F7 delivers superior EMI immunity (lower Crss/Ciss), higher avalanche robustness (+35% E_AS), and better thermal efficiency (−12% R_thj-case), making it optimal for high-density, high-reliability industrial and automotive switching.

Availability

STL130N8F7 is available at Aetrix Electronics and suitable for motor control, DC-DC conversion, and automotive power distribution requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for STL130N8F7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

STL130N8F7 belongs to the STripFET F7 power MOSFET product line, engineered specifically for high-current, high-frequency switching in space-constrained power systems where thermal performance and avalanche reliability are critical.

FAQ

What is the maximum continuous drain current at 100 °C case temperature?

The STL130N8F7 supports 93 A continuous drain current at T_C = 100 °C, as specified in Table 1 of DS9349 Rev 5. This rating is derived from R_thj-case = 1.1 °C/W and T_J(max) = 175 °C, allowing 75 °C temperature rise above case. Derating curves confirm linear reduction from 120 A at 25 °C to 93 A at 100 °C.

Does STL130N8F7 have integrated gate protection?

No, STL130N8F7 does not integrate gate protection diodes or resistors. Its absolute maximum V_GS rating is ±20 V, and gate oxide integrity relies on external design measures - including gate resistor selection (recommended 4.7 Ω), TVS clamping, and layout minimization of parasitic inductance. The device's low Q_gd inherently reduces Miller-induced overvoltage risk.

Can STL130N8F7 be used in paralleled configurations?

Yes - STL130N8F7 supports paralleling due to its positive temperature coefficient of R_DS(on) (confirmed in Figure 10 of DS9349), which promotes current sharing. Successful implementation requires matched gate drive paths, symmetrical PCB layout, and Kelvin-source routing to avoid imbalance. Thermal coupling via shared heatsink further enhances stability.

What is the recommended PCB footprint for thermal performance?

The recommended footprint per Figure 20 (DS9349 Rev 5) uses a 4.2 mm × 4.35 mm central thermal pad with ≥8 thermal vias (0.3 mm diameter, 0.6 mm pitch) connecting to inner-layer ground planes. Minimum copper area is 1 in² (645 mm²) of 2 oz Cu on the bottom layer, ensuring R_thj-pcb remains near the specified 31.3 °C/W under pulsed conditions.