STMicroelectronics STL2N80K5

Overview

STL2N80K5 from STMicroelectronics is an N-channel 800 V, 3.7 Ω typ. R_DS(on), 1.5 A MDmesh™ K5 Power MOSFET in PowerFLAT™ 5x6 VHV package, designed for high-voltage switching in offline SMPS and LED drivers. It features ultra-low gate charge (5 nC), 100% avalanche tested operation, and integrated Zener-protected gate.

For engineers reviewing the STL2N80K5 datasheet, STL2N80K5 pinout, STL2N80K5 application, or STL2N80K5 equivalent, key selection criteria include its 800 V V_(BR)DSS, 3.7 Ω typical on-resistance at V_GS = 10 V, 5 nC total gate charge, 255 ns reverse recovery time, and PowerFLAT™ 5x6 VHV thermal resistance of 3.7 °C/W junction-to-case.

Technical Context

This device employs ST's MDmesh™ K5 vertical superjunction technology to achieve industry-leading R_DS(on) × Q_g figure of merit, enabling high-efficiency operation in hard-switched topologies. Its 800 V breakdown voltage supports universal-input AC/DC designs up to 400 V DC bus.

The integrated back-to-back Zener diodes provide ±30 V gate-source protection (V_(BR)GSO = 30 V), eliminating external clamping components. The source-drain diode exhibits 1.5 V forward voltage at 2 A and 255 ns reverse recovery time at T_j = 25 °C, supporting quasi-resonant and flyback configurations.

Key Specifications

Pinout & Package

STL2N80K5 uses the PowerFLAT™ 5x6 VHV package - a surface-mount, thermally enhanced, 8-terminal leadless package with exposed drain pad for low-inductance, high-current routing and efficient heat transfer to PCB copper.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage power switching applications.

Compared with STP2N80K5 and FQP1N80, STL2N80K5 delivers superior power density via its PowerFLAT™ package, guaranteed avalanche ruggedness for field reliability, and integrated gate protection-making it the preferred choice for space-constrained, safety-certified industrial and metering designs.

Availability

STL2N80K5 is available at Aetrix Electronics and suitable for offline SMPS, LED drivers, AC-DC adapters, and smart meter power supplies requiring stable component supply and long-term industrial lifecycle support.

Supply support for STL2N80K5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering intelligent power, microcontrollers, sensors, and analog solutions for automotive, industrial, and consumer markets.

STL2N80K5 belongs to the MDmesh™ K5 high-voltage MOSFET product line, engineered specifically for high-efficiency, compact AC/DC conversion in energy-efficient lighting, industrial power supplies, and smart infrastructure equipment.

FAQ

What is the maximum continuous drain current at 100 °C case temperature?

The STL2N80K5 supports 1 A continuous drain current at T_C = 100 °C, as specified in Table 2 of the datasheet. This rating is thermally limited by the 3.7 °C/W R_thj-case and maximum 150 °C junction temperature, making it suitable for convection-cooled designs with moderate power dissipation.

Does STL2N80K5 require external gate protection?

No. The device integrates back-to-back Zener diodes between gate and source with a breakdown voltage of 30 V (±10%), as confirmed in Table 8. This eliminates the need for external gate clamping components in standard gate-drive circuits using ≤20 V drive voltage.

Can STL2N80K5 be used in zero-voltage switching (ZVS) topologies?

Yes. With its low 7 pF energy-related output capacitance (C_oss,er) and 105 pF input capacitance, the STL2N80K5 supports ZVS operation in LLC and phase-shifted full-bridge converters up to 300 kHz, provided gate drive strength and resonant tank design accommodate its 5 nC Q_g and 3.7 Ω R_DS(on).

What is the safe operating area (SOA) limitation at 100 µs pulse width?

At 100 µs pulse width, the SOA curve (Figure 2) limits the device to approximately 1.2 A at 400 V V_DS. This is governed by both thermal constraints and secondary breakdown, and must be verified against actual layout parasitics and gate drive rise/fall times to avoid localized hot-spot formation.