STMicroelectronics STL38N65M5

Overview

STL38N65M5 from STMicroelectronics is an N-channel 650 V, 22.5 A Power MOSFET in PowerFLAT™ 8x8 HV package, featuring 0.090 Ω typ. R_DS(on), 710 V V_DS @ T_Jmax, and 71 nC total gate charge. It employs MDmesh™ M5 vertical process technology for high-efficiency switching in offline SMPS and PFC stages.

For engineers reviewing the STL38N65M5 datasheet, STL38N65M5 pinout, STL38N65M5 application, or STL38N65M5 equivalent, key selection criteria include avalanche ruggedness (660 mJ E_AS), low C_oss (74 pF), fast switching (t_d(V) = 66 ns), and thermal resistance (R_thj-case = 0.83 °C/W).

Technical Context

This MOSFET uses ST's MDmesh™ M5 silicon architecture to achieve ultra-low on-resistance while maintaining high voltage blocking capability. Its optimized charge distribution enables reduced switching losses and superior dv/dt immunity (15 V/ns) under hard-switching conditions.

The integrated source-drain diode supports synchronous rectification and inductive load commutation with 354 ns t_rr at 25 °C and 428 ns at 150 °C, enabling robust operation in continuous conduction mode (CCM) PFC and resonant LLC topologies.

Key Specifications

Pinout & Package

STL38N65M5 is housed in a surface-mount PowerFLAT™ 8x8 HV package with exposed drain pad for enhanced thermal performance and mechanical stability. The package features 5 terminals arranged in a single-row configuration with dual-source connections.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage power switching applications.

Compared with IPW65R090CFD7 and IXTH30N65X2, STL38N65M5 delivers superior power density via its 8×8 mm surface-mount package and lower C_oss, making it optimal for space-constrained, high-current PFC and SMPS designs where thermal path efficiency is critical.

Availability

STL38N65M5 is available at Aetrix Electronics and suitable for server power supplies, industrial PFC modules, and telecom rectifiers requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.

Supply support for STL38N65M5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for industrial, automotive, and consumer markets.

This device belongs to ST's MDmesh™ M5 high-voltage Power MOSFET product line, engineered specifically for high-efficiency, high-power-density offline power conversion in datacenter, industrial, and telecom infrastructure.

FAQ

What is the maximum recommended gate drive voltage for STL38N65M5?

The absolute maximum gate-source voltage is ±25 V, but ST specifies 10 V as the standard enhancement voltage for full R_DS(on) conduction. Operating above 15 V provides no significant on-resistance improvement and increases risk of gate oxide stress during transients. A 12–15 V gate drive with active Miller clamp is recommended for robust hard-switching applications.

Can STL38N65M5 be used in synchronous rectification configurations?

No - STL38N65M5 is an N-channel high-side switch intended for primary-side switching only. Its internal body diode is not optimized for synchronous rectification due to relatively high V_SD (1.5 V) and Q_rr (6–8 µC). For secondary-side SR, ST recommends dedicated low-V_F Schottky or logic-level MOSFETs such as STPSC20H12D.

How does the PowerFLAT™ 8x8 HV package affect PCB layout requirements?

The package requires a large, thermally optimized copper pour (≥1 inch², 2 oz Cu) connected directly to pin 5 (Drain) for effective heat dissipation. Vias must be placed within 2 mm of the drain pad perimeter to minimize thermal resistance. Gate and source traces must be tightly coupled and length-matched to suppress common-source inductance, especially in paralleled configurations.

Is avalanche capability tested per unit or batch sample?

ST performs 100% production avalanche testing on every STL38N65M5 unit using unclamped inductive load (UIL) conditions per JEDEC JESD24-11. Each device is stressed at I_AR = 7 A with V_DD = 50 V and verified for parametric integrity post-test, ensuring guaranteed E_AS ≥ 660 mJ without screening exceptions.