Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

STMicroelectronics STL60N10F7

Name: STL60N10F7
Brand: STMicroelectronics
SKU: STL60N10F7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: STL60N10F7

Manufacturer:: STMicroelectronics

Category:: FETs, MOSFETs

Package:: 8-PowerVDFN

Datasheet:: STL60N10F7.pdf

Description:: MOSFET N-CH 100V 46A POWERFLAT

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:14,477

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

STL60N10F7 from STMicroelectronics is an N-channel Power MOSFET in PowerFLAT 5x6 package, designed for high-efficiency switching in DC-DC converters and motor drives. It delivers 100 V V_DS, 14.5 mΩ typ. R_DS(on) at V_GS = 10 V, 12 A continuous current at PCB level, 5 W power dissipation, and features low Crss/Ciss ratio for EMI immunity.

For engineers reviewing the STL60N10F7 datasheet, STL60N10F7 pinout, STL60N10F7 application, or STL60N10F7 equivalent, key selection criteria include its 100 V rating, 14.5 mΩ on-resistance, 25 nC total gate charge, avalanche ruggedness, and thermal performance on FR-4 PCBs.

Technical Context

This device employs ST's STripFET F7 DeepGATE trench-gate technology to minimize R_DS(on) while reducing C_iss (1640 pF typ.) and Q_g (25 nC typ.), enabling fast switching with low conduction and switching losses. Its low Crss/Ciss ratio (25/1640 ≈ 0.015) suppresses Miller-induced turn-on risk under high dv/dt conditions.

The MOSFET supports unclamped inductive switching with guaranteed avalanche energy rating, operates up to 175 °C junction temperature, and is characterized for both case-mounted (R_thj-case = 2.08 °C/W) and PCB-mounted (R_thj-pcb = 31 °C/W) thermal configurations.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	100 V - Supports 48 V bus systems with 2× safety margin against transients.
R_DS(on) max	18 mΩ - Ensures ≤2.6 W conduction loss at 12 A, critical for thermally constrained PCB layouts.
I_D (T_pcb = 25 °C)	12 A - Rated for sustained current delivery on standard 1-inch² FR-4 board with 2 oz Cu.
Q_g	25 nC - Enables efficient gate driving with moderate-current drivers (e.g., 1–2 A peak).
C_rss/C_iss	25/1640 pF - Low ratio improves noise immunity and reduces false triggering in noisy environments.
T_J max	175 °C - Allows operation in automotive under-hood or industrial ambient temperatures up to 125 °C.
E_AS	Guaranteed avalanche ruggedness - Eliminates need for external snubbers in inductive load switching.

Pinout & Package

STL60N10F7 uses the surface-mount PowerFLAT 5x6 package (type R), optimized for high-power density and thermal transfer to PCB copper. The exposed drain pad occupies pins 5–8 and serves as primary heat path; gate is pin 4; source connects to pins 1–3.

Pin/Terminal	Circuit Role	Design Meaning
D (5, 6, 7, 8)	Drain	Exposed metal pad - electrically and thermally connected to drain; must be soldered to large PCB copper pour for thermal management.
G (4)	Gate	Control terminal - requires low-impedance drive due to 25 nC Q_g; sensitive to ESD (±20 V absolute max).
S (1, 2, 3)	Source	Reference node for gate drive and current sensing; tied to PCB ground plane for low-inductance return path.

Key Features

Feature	Design Value
Ultra-low R_DS(on)	14.5 mΩ typ. at V_GS = 10 V - Reduces I²R losses by >30% vs. legacy F6 devices in same package.
Low Crss/Ciss ratio	25/1640 pF - Minimizes Miller feedback, enabling robust operation in hard-switching topologies without gate clamping.
High avalanche energy rating	Guaranteed unclamped inductive switching - Supports reliable operation in relay drivers and solenoid controls without external protection.
Optimized for PCB thermal dissipation	R_thj-pcb = 31 °C/W on 1-inch² FR-4 - Enables 5 W continuous power handling without heatsink in space-constrained designs.
Enhanced trench gate structure	STripFET F7 DeepGATE - Improves cell density and reduces gate charge while maintaining ruggedness.

Applications

DC-DC Synchronous Buck Converter

Automotive Body Control Module (BCM)

Use Scenario: High-efficiency 12 V → 3.3 V/5 V conversion for infotainment and ADAS ECUs.

IC Role / Device Role: High-side synchronous rectifier switch in buck regulator stage.

Use Value: 14.5 mΩ R_DS(on) minimizes conduction loss at 10–12 A load, improving efficiency by ≥1.2% over 25 mΩ alternatives.

Use Scenario: Load switching for interior lighting, window lifters, and HVAC actuators.

IC Role / Device Role: Low-side driver for 12 V inductive and resistive loads.

Use Value: Guaranteed avalanche capability eliminates need for freewheeling diodes in relay/solenoid interfaces, reducing BOM count.

Industrial Motor Drive Half-Bridge

Server PSU OR-ing FET

Use Scenario: 24–48 V BLDC motor control in pumps and fans.

IC Role / Device Role: Low-side switch in half-bridge configuration with fast 8 ns fall time.

Use Value: 25 nC Q_g and 17 ns rise time enable <100 kHz PWM operation with minimal gate drive loss.

Use Scenario: Hot-swap and redundancy management in 48 V server power distribution.

IC Role / Device Role: OR-ing MOSFET in ideal diode configuration.

Use Value: Low 1.1 V V_SD forward drop at 12 A reduces conduction loss vs. Schottky diodes, improving system efficiency by ~0.8 W per FET.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel 100 V power MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IPB120N10N3 G	R_DS(on) = 12.5 mΩ typ., Q_g = 32 nC, TO-263 package	Larger footprint and higher gate charge increase layout area and drive complexity	Preferred only when case-mounted thermal path (R_thj-case = 1.4 °C/W) is required over PCB mounting
IRF3205PBF	R_DS(on) = 40 mΩ typ., TO-220 package, no avalanche rating	Higher conduction loss and lack of guaranteed avalanche limit use in inductive switching	Acceptable only in low-frequency, non-avalanche-critical linear or switching applications with ample heatsinking

Compared with IPB120N10N3 G and IRF3205PBF, STL60N10F7 offers superior power density and EMI robustness via its low Crss/Ciss ratio and PowerFLAT 5x6 thermal interface-critical for compact, high-reliability PCB-mounted designs.

Availability

STL60N10F7 is available at Aetrix Electronics and suitable for DC-DC converters, automotive body control modules, and industrial motor drives requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for STL60N10F7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for automotive, industrial, and consumer markets.

STL60N10F7 belongs to the STripFET F7 family-engineered specifically for high-efficiency, high-density power conversion in space-constrained applications where PCB-level thermal management dominates over heatsink-based cooling.

FAQ

What is the maximum continuous drain current for STL60N10F7 at 100 °C PCB temperature?

The datasheet specifies I_D = 9 A continuous at T_pcb = 100 °C (Table 1). This rating assumes mounting on a 1-inch² FR-4 board with 2 oz copper and accounts for R_thj-pcb = 31 °C/W. Exceeding this current risks junction temperature exceeding 175 °C under steady-state conditions.

Does STL60N10F7 have a built-in body diode, and what are its recovery characteristics?

Yes-it integrates a source-drain diode rated for 12 A continuous and 48 A pulsed. At T_J = 150 °C, it exhibits t_rr = 53 ns, Q_rr = 67 nC, and I_RRM = 2.5 A under specified test conditions (V_DD = 50 V, di/dt = 100 A/µs), making it suitable for synchronous rectification and flyback recovery.

Can STL60N10F7 be driven directly from a 3.3 V microcontroller GPIO?

No-its V_GS(th) ranges from 2.5 V to 4.5 V, but full enhancement requires V_GS ≥ 10 V to achieve 14.5 mΩ R_DS(on). A 3.3 V drive yields high on-resistance (>100 mΩ) and excessive conduction loss; a dedicated gate driver or level-shifting circuit is mandatory.

What is the recommended PCB footprint for thermal reliability?

Per Figure 20 in DS9584 Rev 4, the recommended footprint uses a 4.8 × 4.8 mm thermal pad centered under the device, connected to ≥4 thermal vias (0.3 mm diameter, 0.8 mm pitch) to inner-layer copper pours. Minimum solder mask opening matches the exposed drain pad (D5/D6 dimensions), ensuring full solder wetting for optimal R_thj-pcb.

STL60N10F7 Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: DeepGATE™, STripFET™ VII

Package/Case:: 8-PowerVDFN

Packaging:: Tape & Reel (TR)

Product Status:: Active

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 100 V

Current - Continuous Drain (Id) @ 25°C:: 46A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 10V

Rds On (Max) @ Id, Vgs:: 18mOhm @ 6A, 10V

Vgs(th) (Max) @ Id:: 4.5V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 25 nC @ 10 V

Vgs (Max):: 20V

Input Capacitance (Ciss) (Max) @ Vds:: 1640 pF @ 50 V

FET Feature:: -

Power Dissipation (Max):: 5W (Ta), 72W (Tc)

Operating Temperature:: -55°C ~ 175°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: PowerFlat™ (5x6)

STL60N10F7 FAQ

1.How can I place an order for STL60N10F7 through Aetrix?

Please submit a Request for Quotation (RFQ) for STL60N10F7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for STL60N10F7 reliable?

The price and inventory of STL60N10F7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STL60N10F7 is usually 5 days.

3.What payment methods are accepted for STL60N10F7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STL60N10F7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for STL60N10F7?

STL60N10F7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your STL60N10F7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for STL60N10F7?

For technical support, including STL60N10F7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STL60N10F7 requirements.

6.How does Aetrix verify that STL60N10F7 is sourced from the original manufacturer or authorized distributors?

All STL60N10F7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STL60N10F7 meets industry standards.

7.What is the process for return or replacement of STL60N10F7?

All STL60N10F7 units undergo pre-shipment inspection (PSI). If there is an issue with STL60N10F7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The STL60N10F7 part is unused and in its original packaging.

Return procedure for STL60N10F7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…