STMicroelectronics STL7DN6LF3
- Part No.:
- STL7DN6LF3
- Manufacturer:
- STMicroelectronics
- Category:
- FET, MOSFET Arrays
- Package:
- 8-PowerVDFN
- Datasheet:
-
STL7DN6LF3.pdf
- Description:
- MOSFET 2N-CH 60V 20A POWERFLAT
- Quantity:
- Payment:

- Shipping:

Inventory:14,488
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Product details
Overview
STL7DN6LF3 from STMicroelectronics is an automotive-grade dual N-channel 60 V Power MOSFET in PowerFLAT™ 5x6 double island package, featuring 35 mΩ typ. RDS(on) at VGS = 10 V, 6.5 A continuous drain current (Tpcb = 25 °C), and AEC-Q101 qualification for under-hood switching applications including motor control and DC-DC converters.
For engineers reviewing the STL7DN6LF3 datasheet, STL7DN6LF3 pinout, STL7DN6LF3 application, or STL7DN6LF3 equivalent, key selection criteria include logic-level gate drive compatibility (VGS(th) = 1–2.5 V), wettable flank package for automated optical inspection, 175 °C junction temperature rating, and 100% unclamped inductive avalanche ruggedness (EAS = 190 mJ).
Technical Context
This dual N-channel MOSFET integrates two identical silicon dice in a single PowerFLAT™ 5x6 double island thermally enhanced package, enabling independent high-side/low-side switching or parallel operation. Its STripFET™ F3 process delivers low gate charge (Qg = 8.7 nC typ.) and optimized capacitance profile (Ciss = 432 pF, Crss = 10.5 pF) for fast, low-loss switching up to 100 kHz.
The device supports logic-level drive with VGS(th) as low as 1 V, ensuring full enhancement with 3.3 V or 5 V microcontroller outputs. Thermal design is enabled by Rthj-case = 2.9 °C/W and Rthj-pcb = 35 °C/W (FR-4, 1 in², 2 oz Cu), supporting high-power density layouts in space-constrained automotive modules.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 60 V - Supports 48 V automotive systems with 20 % margin against load dump transients. |
| RDS(on) max | 43 mΩ @ VGS = 10 V - Limits conduction loss to ≤2.8 W at 6.5 A continuous current. |
| ID cont (Tpcb = 25 °C) | 6.5 A - Rated for sustained operation on standard PCBs without heatsink. |
| Qg | 8.7 nC typ. - Enables efficient 100 kHz PWM switching with <1 µs total transition time. |
| TJ max | 175 °C - Qualified for engine bay environments per AEC-Q101 Grade 0. |
| EAS | 190 mJ - Withstands unclamped inductive turn-off events without failure (VDD = 25 V, ID = 8 A). |
| VGS(th) | 1–2.5 V - Ensures reliable turn-on with 3.3 V GPIO or automotive logic drivers. |
Pinout & Package
STL7DN6LF3 uses the PowerFLAT™ 5x6 double island package (wettable flank variant), measuring 5.2 × 6.2 mm with 0.8 mm height. The dual-die layout features two electrically isolated source-drain-gate structures sharing a common thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 (Top side) | Source 1 / Drain 1 / Gate 1 / Source 2 | Pins 1–4 correspond to first MOSFET: S1–D1–G1–S2; enables independent control of two channels. |
| 5, 6, 7, 8 (Bottom side) | Drain 2 / Gate 2 / Thermal Pad / NC | Pins 5–6 are D2/G2; Pin 7 is exposed thermal pad (connected to both sources); Pin 8 not connected. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q101 qualified | Validated for automotive use across -55 °C to +175 °C, including temperature cycling and HTRB. |
| Wettable flank leads | Enables automated solder joint inspection (AOI) on bottom-side pins for high-reliability assembly. |
| 100% avalanche rated | Guaranteed energy handling (EAS = 190 mJ) eliminates need for external snubbers in inductive loads. |
| Logic-level gate threshold | VGS(th) down to 1 V ensures full enhancement with 3.3 V MCUs, reducing gate driver complexity. |
| Low Qgd/Qgs ratio | Qgd = Qgs = 1.9 nC - Minimizes Miller effect, improving noise immunity during high-dv/dt switching. |
Applications
| Automotive Body Control Module (BCM) | 48 V Mild Hybrid DC-DC Converter |
|---|---|
Use Scenario: Driving solenoids, relays, and LED arrays in door modules and lighting control units. IC Role / Device Role / Timing Role: Dual-channel power switch providing independent high-side and low-side control with fast turn-on (<17 ns total delay+rise). Use Value: Eliminates need for discrete level shifters or dedicated high-side drivers due to logic-level VGS(th) and integrated dual topology. | Use Scenario: Synchronous rectification in bidirectional buck-boost stages converting 48 V to 12 V/14 V. IC Role / Device Role / Timing Role: Low-side switch in synchronous rectifier pair, leveraging low RDS(on) (35 mΩ typ.) and fast fall time (5.4 ns). Use Value: Reduces conduction loss by 35 % vs. comparable 60 V MOSFETs, improving converter efficiency above 95 % at 5 A output. |
| Electric Power Steering (EPS) Motor Driver | Automotive HVAC Blower Control |
Use Scenario: Half-bridge leg in three-phase inverter driving 12 V brushed or BLDC assist motors. IC Role / Device Role / Timing Role: High-current switching element with 26 A pulsed capability (IDM) and robust avalanche performance. Use Value: Survives fault conditions (e.g., phase-to-phase short) without desaturation protection circuitry, simplifying gate driver design. | Use Scenario: PWM-controlled fan speed regulation in climate control systems. IC Role / Device Role / Timing Role: Low-side switch modulating motor current at 20–25 kHz to eliminate audible noise. Use Value: Low Qg (8.7 nC) and fast switching (td(off) = 32.4 ns) minimize switching losses at high PWM frequencies. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual N-channel 60 V power switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon BSC020N06NS3 | Single-channel, 2.0 mΩ RDS(on), no wettable flanks, TO-263 package | Requires two devices and larger board area; lacks AEC-Q101 grade 0 rating | Preferred only when ultra-low RDS(on) justifies added cost and footprint. |
| ON Semiconductor NTMFS5C675NL | Dual-channel, 5.2 mΩ RDS(on), Power56 package, no AEC-Q101 certification | Higher conduction loss at 6.5 A; unsuitable for under-hood deployment without derating | Acceptable for cabin-mounted non-safety-critical loads where temperature range is limited. |
Compared with BSC020N06NS3 and NTMFS5C675NL, STL7DN6LF3 uniquely combines dual-channel integration, AEC-Q101 Grade 0 qualification, wettable flank inspection capability, and balanced 35 mΩ/8.7 nC performance-making it optimal for space- and reliability-constrained automotive power stages.
Availability
STL7DN6LF3 is available at Aetrix Electronics and suitable for automotive body control modules, 48 V mild hybrid converters, and electric power steering systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for STL7DN6LF3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and sensor solutions for automotive, industrial, and consumer markets.
The STL7DN6LF3 belongs to ST's STripFET™ F3 automotive power MOSFET product line, engineered specifically for high-reliability, high-efficiency switching in engine compartment and chassis applications where thermal robustness and AEC-Q101 compliance are mandatory.
FAQ
What is the maximum continuous drain current for STL7DN6LF3 at 100 °C PCB temperature?
At Tpcb = 100 °C, the STL7DN6LF3 supports 4.6 A continuous drain current per channel, as specified in Table 2 of the datasheet. This rating accounts for thermal resistance to PCB (Rthj-pcb = 35 °C/W) and assumes a 1 in² FR-4 board with 2 oz copper. Derating is linear between 25 °C and 100 °C.
Does STL7DN6LF3 support gate drive from a 3.3 V microcontroller?
Yes. With a gate threshold voltage range of 1–2.5 V and guaranteed turn-on at VGS = 4.5 V (RDS(on) ≤ 60 mΩ), the STL7DN6LF3 fully enhances using standard 3.3 V GPIO outputs. Its low Qg (8.7 nC) further ensures minimal gate drive power requirement.
How is the thermal pad (Pin 7) intended to be connected on the PCB?
Pin 7 is the exposed thermal pad, internally connected to both source terminals. It must be soldered to a large copper pour tied to the system ground plane. Minimum recommended footprint matches Figure 20: 3.5 × 3.7 mm with thermal vias (≥6×0.3 mm) to inner ground layers for optimal Rthj-pcb performance.
Is STL7DN6LF3 pin-compatible with other PowerFLAT™ 5x6 dual MOSFETs?
No. STL7DN6LF3 has a unique 8-pin dual-island configuration (S1-D1-G1-S2/D2-G2-Thermal-NC). It is not pin-compatible with single-channel PowerFLAT™ 5x6 devices (e.g., STL220N6LF3) or alternate dual variants like STP7DN6L. Layout must follow Figure 18 or 19 exactly.
STL7DN6LF3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- STripFET™ III
- Package/Case:
- 8-PowerVDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- MOSFET (Metal Oxide)
- Configuration:
- 2 N-Channel (Dual)
- FET Feature:
- Logic Level Gate
- Drain to Source Voltage (Vdss):
- 60V
- Current - Continuous Drain (Id) @ 25°C:
- 20A
- Rds On (Max) @ Id, Vgs:
- 43mOhm @ 3A, 10V
- Vgs(th) (Max) @ Id:
- 3V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 8.8nC @ 10V
- Input Capacitance (Ciss) (Max) @ Vds:
- 432pF @ 25V
- Power - Max:
- 52W
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerFlat™ (5x6)
STL7DN6LF3 FAQ
1.How can I place an order for STL7DN6LF3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STL7DN6LF3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STL7DN6LF3 reliable?
The price and inventory of STL7DN6LF3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STL7DN6LF3 is usually 5 days.
3.What payment methods are accepted for STL7DN6LF3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STL7DN6LF3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STL7DN6LF3?
STL7DN6LF3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STL7DN6LF3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STL7DN6LF3?
For technical support, including STL7DN6LF3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STL7DN6LF3 requirements.
6.How does Aetrix verify that STL7DN6LF3 is sourced from the original manufacturer or authorized distributors?
All STL7DN6LF3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STL7DN6LF3 meets industry standards.
7.What is the process for return or replacement of STL7DN6LF3?
All STL7DN6LF3 units undergo pre-shipment inspection (PSI). If there is an issue with STL7DN6LF3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STL7DN6LF3 part is unused and in its original packaging.
Return procedure for STL7DN6LF3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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