STMicroelectronics STP10N60M2
- Part No.:
- STP10N60M2
- Manufacturer:
- STMicroelectronics
- Category:
- FETs, MOSFETs
- Package:
- TO-220-3
- Datasheet:
-
STP10N60M2.pdf
- Description:
- MOSFET N-CH 600V 7.5A TO220
- Quantity:
- Payment:

- Shipping:

Inventory:689
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Product details
Overview
STP10N60M2 from STMicroelectronics is an N-channel 600 V, 0.55 Ω typ. (0.60 Ω max.) MDmesh™ M2 Power MOSFET in TO-220 package, rated for 7.5 A continuous drain current at 25 °C and 100% avalanche tested. It features extremely low gate charge (13.5 nC), optimized output capacitance profile (Coss = 22 pF), and Zener-protected gate, making it suitable for high-efficiency 400–600 V flyback and PFC converters in industrial power supplies.
For engineers reviewing the STP10N60M2 datasheet, STP10N60M2 pinout, STP10N60M2 application, or STP10N60M2 equivalent, key selection criteria include RDS(on) stability over temperature, dv/dt ruggedness (50 V/ns), unclamped inductive switching capability (EAS = 110 mJ), and thermal resistance (RthJC = 1.47 °C/W) for conduction-loss-sensitive SMPS designs.
Technical Context
This device uses ST's MDmesh M2 strip layout and enhanced vertical structure to achieve low on-resistance while maintaining fast switching performance. Its Coss eq. of 83 pF (0–480 V) and Crss of 0.84 pF support high-frequency operation with reduced switching loss and improved EMI behavior in hard-switched topologies.
The integrated source-drain diode exhibits trr = 270 ns (TJ = 25 °C) and Qrr = 2.0 µC under standard test conditions, enabling reliable operation in discontinuous conduction mode (DCM) PFC stages without external snubbing. Gate threshold voltage is tightly specified (2–4 V) and stable across –50 to 125 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS max | 600 V - Withstands 480 V DC bus with 20% margin; supports universal-input offline SMPS up to 265 VAC. |
| RDS(on) typ. | 0.55 Ω @ VGS = 10 V, ID = 3 A - Enables <1.2 W conduction loss at 7.5 A, critical for thermally constrained TO-220 layouts. |
| Qg | 13.5 nC - Reduces gate drive power and enables use of low-cost 1-A drivers in 100–300 kHz converters. |
| Coss | 22 pF @ VDS = 100 V - Low stored energy (Eoss ≈ 0.5 × Coss × V²) minimizes turn-on loss in ZVS-influenced circuits. |
| EAS | 110 mJ - Guarantees robustness against single-pulse inductive transients in motor drives and UPS hold-up stages. |
| dv/dt ruggedness | 50 V/ns - Prevents false turn-on during high-slew-rate switching events in bridge-leg configurations. |
| TJ range | –55 to 150 °C - Supports operation in sealed industrial enclosures without active cooling. |
Pinout & Package
TO-220 package (Type A) with isolated tab; metal tab is electrically connected to the drain (D). Standard 3-pin through-hole mounting with 2.54 mm lead pitch and 13–14 mm body length.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (Left) | Gate (G) | High-impedance control input; requires ≤±25 V gate-source voltage; 6.4 Ω intrinsic gate resistance limits ringing. |
| 2 (Center) | Drain (D) / Tab | Main high-voltage power terminal; tab must be electrically isolated from heatsink unless referenced to same potential as drain. |
| 3 (Right) | Source (S) | Power return path and gate reference node; connects directly to PCB ground plane for low-inductance switching loop. |
Key Features
| Feature | Design Value |
|---|---|
| MDmesh M2 technology | Combines low RDS(on) and low Coss via optimized cell pitch and epitaxial layer grading-enables >94% efficiency in 65 kHz PFC stages. |
| Zener-protected gate | Integrated gate-body Zener clamps transient overvoltage to ±25 V, eliminating need for external gate protection in noisy industrial environments. |
| 100% avalanche tested | Each unit validated for repetitive and non-repetitive avalanche stress per JEDEC JESD24-11, ensuring field reliability in unclamped inductive loads. |
| Low Qgd/Qg ratio | 7.2 nC / 13.5 nC = 0.53 - Minimizes Miller plateau duration, improving controllability during hard switching and reducing risk of shoot-through. |
| Optimized Coss profile | Coss remains stable across 0–480 V (Cosseq = 83 pF), enabling predictable soft-switching timing in LLC resonant converters. |
Applications
| Industrial AC-DC Power Supplies | Server & Telecom Rectifiers |
|---|---|
|
Use Scenario: 600 W active clamp forward converter with 400 V DC bus and 100 kHz switching frequency. IC Role / Device Role / Timing Role: Primary-side high-side switch handling full input voltage swing and delivering regulated 12 V/50 A output. Use Value: 0.55 Ω RDS(on) and 13.5 nC Qg reduce total switching + conduction loss to <4.2 W, enabling natural convection cooling. |
Use Scenario: Three-phase rectifier stage in 3 kW telecom PSU with interleaved PFC and 65 kHz operation. IC Role / Device Role / Timing Role: Fast-recovery boost switch in each PFC leg, operating in DCM with zero-current turn-on. Use Value: 270 ns trr and 2.0 µC Qrr minimize reverse recovery loss and eliminate need for SiC diode co-packaging. |
| UPS Hold-Up Circuits | Motor Drive Inverters |
|
Use Scenario: 1.5 kVA online UPS with 480 V DC link and battery backup switching. IC Role / Device Role / Timing Role: DC-link switch controlling battery-to-bus energy transfer during mains failure. Use Value: 110 mJ EAS withstands 20 ms inductive kickback from transformer-coupled hold-up chokes without failure. |
Use Scenario: 750 W BLDC inverter for HVAC compressor with 20 kHz PWM and regenerative braking. IC Role / Device Role / Timing Role: Low-side switching element in 3-phase bridge, conducting freewheeling current during PWM off-time. Use Value: Zener-protected gate survives 400 V/ns common-mode transients induced by adjacent IGBT switching in compact PCB layouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel 600 V power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STP12N60M2 | Higher ID (8.5 A), higher RDS(on) (0.52 Ω typ.), same Qg (13.5 nC), identical TO-220 package | Marginally better current handling but slightly lower voltage margin (V(BR)DSS = 600 V same); not recommended for 480 V bus with aging derating | Select only if peak load current exceeds 7.5 A and thermal headroom allows higher RDS(on)-related loss. |
| FDPF12N60NZ | Lower RDS(on) (0.51 Ω typ.), higher Qg (22 nC), different TO-220FP package with insulated tab | Requires insulated mounting hardware; higher gate drive loss reduces efficiency above 150 kHz | Prefer when board-level isolation is mandatory and switching frequency <120 kHz; avoid in space-constrained heatsink designs. |
Compared with STP12N60M2, STP10N60M2 offers tighter V(BR)DSS distribution and lower EMI due to reduced Crss, while FDPF12N60NZ trades gate drive simplicity for marginally lower conduction loss-making STP10N60M2 optimal for cost-sensitive, thermally constrained 100–200 kHz industrial SMPS.
Availability
STP10N60M2 is available at Aetrix Electronics and suitable for industrial AC-DC power supplies, telecom rectifiers, and UPS hold-up circuits requiring stable component supply and long-term manufacturing continuity.
Supply support for STP10N60M2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.
STP10N60M2 belongs to the MDmesh M2 high-voltage power MOSFET product line, engineered specifically for high-efficiency, high-reliability switched-mode power conversion in 400–600 V applications.
FAQ
What is the maximum continuous drain current at 100 °C case temperature?
The STP10N60M2 supports 4.9 A continuous drain current at TC = 100 °C, as specified in Table 1 of DS9703 Rev 5. This derating reflects junction-to-case thermal resistance (1.47 °C/W) and maximum TJ of 150 °C, enabling reliable operation in forced-air-cooled industrial enclosures.
Does STP10N60M2 have integrated gate protection?
Yes-STP10N60M2 integrates a Zener diode between gate and source to clamp transient overvoltage to ±25 V, as confirmed in the "Features" section of DS9703. This eliminates the need for external gate protection components in typical industrial noise environments.
Can STP10N60M2 replace STP10NK60Z in existing designs?
No-STP10NK60Z uses older SuperMESH technology with higher RDS(on) (0.75 Ω), higher Qg (35 nC), and no Zener gate protection. Direct replacement would increase conduction loss by ~36% and switching loss by ~62%, requiring gate driver and thermal redesign.
What is the safe operating area (SOA) limitation at 100 µs pulse width?
At tp = 100 µs, the SOA for TO-220 package is limited to 3.5 A at 400 V (Figure 1, DS9703 Rev 5), governed by RDS(on) and thermal inertia. This defines maximum single-pulse surge capability in short-circuit fault conditions before thermal runaway occurs.
STP10N60M2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- MDmesh™ II Plus
- Package/Case:
- TO-220-3
- Packaging:
- Tube
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 600 V
- Current - Continuous Drain (Id) @ 25°C:
- 7.5A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 600mOhm @ 3A, 10V
- Vgs(th) (Max) @ Id:
- 4V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 13.5 nC @ 10 V
- Vgs (Max):
- ±25V
- Input Capacitance (Ciss) (Max) @ Vds:
- 400 pF @ 100 V
- FET Feature:
- -
- Power Dissipation (Max):
- 85W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- TO-220
STP10N60M2 FAQ
1.How can I place an order for STP10N60M2 through Aetrix?
Please submit a Request for Quotation (RFQ) for STP10N60M2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STP10N60M2 reliable?
The price and inventory of STP10N60M2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STP10N60M2 is usually 5 days.
3.What payment methods are accepted for STP10N60M2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STP10N60M2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STP10N60M2?
STP10N60M2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STP10N60M2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STP10N60M2?
For technical support, including STP10N60M2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STP10N60M2 requirements.
6.How does Aetrix verify that STP10N60M2 is sourced from the original manufacturer or authorized distributors?
All STP10N60M2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STP10N60M2 meets industry standards.
7.What is the process for return or replacement of STP10N60M2?
All STP10N60M2 units undergo pre-shipment inspection (PSI). If there is an issue with STP10N60M2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STP10N60M2 part is unused and in its original packaging.
Return procedure for STP10N60M2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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