STMicroelectronics STP18N65M5
- Part No.:
- STP18N65M5
- Manufacturer:
- STMicroelectronics
- Category:
- FETs, MOSFETs
- Package:
- TO-220-3
- Datasheet:
-
STP18N65M5.pdf
- Description:
- MOSFET N-CH 650V 15A TO220
- Quantity:
- Payment:

- Shipping:

Inventory:883
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Product details
Overview
STP18N65M5 from STMicroelectronics is an N-channel 650 V, 15 A Power MOSFET in TO-220 package, fabricated with MDmesh M5 vertical process technology. It delivers 198 mΩ typical RDS(on), 15 V/ns dv/dt capability, and 210 mJ single-pulse avalanche energy - optimized for high-efficiency AC-DC power supplies and industrial SMPS.
For engineers reviewing the STP18N65M5 datasheet, STP18N65M5 pinout, STP18N65M5 application, or STP18N65M5 equivalent, key selection criteria include its 650 V VDS, 1.14 °C/W RthJC, 31 nC total gate charge, and 100% avalanche-tested ruggedness for reliable high-voltage switching.
Technical Context
This MOSFET employs ST's MDmesh M5 silicon process to achieve ultra-low on-resistance while maintaining high voltage blocking (650 V) and fast switching dynamics. Its 3.2 pF Crss and 1240 pF Ciss enable efficient hard-switching at high frequencies up to several hundred kHz.
The integrated body diode exhibits 290 ns trr and 3.4 µC Qrr at 25 °C, supporting synchronous rectification and ZVS-capable topologies. Thermal design is enabled by low junction-to-case resistance (1.14 °C/W) and 150 °C maximum junction temperature rating.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 650 V - supports primary-side switching in universal-input offline SMPS up to 400 V DC bus with margin. |
| RDS(on) max | 220 mΩ - limits conduction loss to ≤2.5 W at 7.5 A continuous drain current (TC = 25 °C). |
| ID cont | 15 A @ TC = 25 °C - enables 300–500 W power stages with forced-air cooling. |
| EAS | 210 mJ - withstands unclamped inductive switching events without failure in flyback or LLC resonant converters. |
| Qg | 31 nC - determines gate drive power requirement (~155 µW per MHz of switching frequency at 10 V VGS). |
| dv/dt | 15 V/ns - ensures immunity to false turn-on during high-slew-rate transients in bridge configurations. |
| RthJC | 1.14 °C/W - allows 96 W dissipation before reaching 150 °C junction limit under ideal heatsinking. |
Pinout & Package
STP18N65M5 is housed in a TO-220 type A package with isolated tab (drain-connected), standard 3-pin through-hole configuration, and RoHS-compliant ECOPACK2 finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| G (Pin 1) | Gate | Controls channel conduction; requires ≥10 V VGS for full enhancement; 3 Ω intrinsic gate resistance affects drive loop damping. |
| D (Pin 2 / Tab) | Drain | Main high-voltage terminal; electrically connected to metal tab - must be insulated from heatsink unless referenced to same potential. |
| S (Pin 3) | Source | Power return path and gate reference; source inductance directly impacts switching speed and ringing in high-di/dt applications. |
Key Features
| Feature | Design Value |
|---|---|
| MDmesh M5 silicon process | Delivers 198 mΩ typ. RDS(on) at 650 V - 25% lower than prior-generation MDmesh devices for identical die area. |
| 100% avalanche tested | Guarantees single-pulse EAS ≥210 mJ - eliminates need for external snubbers in clamp-based topologies. |
| Low Crss (3.2 pF) | Reduces Miller-induced turn-off delay and improves noise immunity in half-bridge gate drive layouts. |
| Fast body diode (trr = 290 ns) | Enables use in quasi-resonant flyback and active clamp forward converters without external Schottky replacement. |
| High dv/dt immunity (15 V/ns) | Prevents spurious turn-on during commutation in phase-shifted full-bridge or LLC circuits operating above 100 kHz. |
Applications
| Industrial SMPS | Server PSU Primary Switch |
|---|---|
Use Scenario: 800 W open-frame power supply for PLC controllers operating from 85–264 VAC input. IC Role / Device Role / Timing Role: Primary-side high-side switch in continuous conduction mode (CCM) PFC + LLC resonant stage. Use Value: 220 mΩ RDS(on) reduces conduction loss by 1.8 W vs. legacy 600 V MOSFETs, improving full-load efficiency from 92.1% to 93.4%. | Use Scenario: 1.5 kW redundant server power supply with digital control and PMBus interface. IC Role / Device Role / Timing Role: Main switching device in asymmetric half-bridge topology driving resonant tank at 250–500 kHz. Use Value: 15 V/ns dv/dt rating prevents false triggering during rapid bus voltage transitions, eliminating gate driver desaturation faults. |
| EV Onboard Charger | Telecom Rectifier Module |
Use Scenario: Bidirectional 6.6 kW OBC using dual active bridge (DAB) architecture with SiC diode synchronization. IC Role / Device Role / Timing Role: Low-side switch in secondary-side DAB leg handling 350 V DC link and 20 kHz phase-shift modulation. Use Value: 31 nC Qg enables gate drive with <1 W loss using discrete 2 A peak drivers, reducing thermal load on auxiliary supply. | Use Scenario: 3 kW -48 V telecom rectifier with hold-up capacitor support and hot-swap capability. IC Role / Device Role / Timing Role: Primary switch in forward converter with active clamp reset, operating at 200 kHz with 50% duty cycle. Use Value: 210 mJ EAS absorbs clamp energy spikes during transient overloads, preventing catastrophic failure without added TVS protection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage power switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STW18N65M5 | Same silicon die, but in TO-247 package with lower RthJA (50 °C/W vs. 62.5 °C/W) and higher PTOT (150 W vs. 110 W). | Preferred for >500 W designs requiring higher power density and improved thermal headroom. | Select STW18N65M5 when board space permits TO-247 and thermal budget exceeds 90 W dissipation. |
| IPP65R220CFD7 | Infineon CoolMOS CFD7: 220 mΩ max RDS(on), 650 V, but higher Qg (42 nC) and slower trr (420 ns). | Less suitable for high-frequency ZVS or critical dv/dt environments due to higher gate charge and diode recovery lag. | Choose only if existing PCB layout uses Infineon footprint and system operates below 150 kHz with soft-switching. |
Compared with STW18N65M5, STP18N65M5 trades 40 W thermal headroom and 12.5 °C/W higher RthJA for TO-220 compatibility and lower assembly cost; versus IPP65R220CFD7, it offers superior diode recovery and dv/dt immunity at identical RDS(on), enabling tighter timing margins in resonant topologies.
Availability
STP18N65M5 is available at Aetrix Electronics and suitable for industrial SMPS, server power supplies, EV onboard chargers, and telecom rectifier modules requiring stable component supply across multi-year production cycles.
Supply support for STP18N65M5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and sensor solutions for automotive, industrial, and consumer markets.
This device belongs to ST's MDmesh M5 high-voltage Power MOSFET product line, engineered specifically for high-efficiency, high-reliability offline power conversion systems operating up to 650 V.
FAQ
What is the maximum safe operating temperature for STP18N65M5?
The absolute maximum junction temperature is 150 °C. Operation above this threshold risks permanent degradation of the silicon die and bond wires. Derating is required above 25 °C case temperature: continuous current drops to 9.4 A at TC = 100 °C per datasheet Table 1. Thermal design must ensure RthJC + RthCS + RthSA keeps TJ ≤145 °C under worst-case load and ambient conditions.
Does STP18N65M5 require a negative gate voltage for reliable turn-off?
No. The device is fully enhanced at VGS = 10 V and has a gate threshold voltage range of 3–5 V. While −5 V to 0 V gate drive improves noise immunity in high-dv/dt environments, it is not required for functional operation. Gate drive circuits must maintain VGS ≤ ±25 V to avoid gate oxide damage per absolute maximum ratings.
Can STP18N65M5 replace older STP18N60M2 in existing designs?
Yes, with qualification. STP18N65M5 offers higher VDS (650 V vs. 600 V), lower RDS(on) (220 mΩ vs. 280 mΩ), and improved avalanche ruggedness (210 mJ vs. 120 mJ). Layout changes are unnecessary since both use TO-220 packages with identical pinout, but gate drive strength should be verified due to higher Qg (31 nC vs. 24 nC).
Is the TO-220 tab electrically isolated in STP18N65M5?
Yes. The metal tab is internally connected to the drain terminal and is electrically isolated from the leadframe per TO-220 type A mechanical specification. When mounted to a heatsink, an insulating washer or pad must be used unless the heatsink is at the same potential as the drain node - critical for primary-side isolation in offline converters.
STP18N65M5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- MDmesh™ V
- Package/Case:
- TO-220-3
- Packaging:
- Tube
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 650 V
- Current - Continuous Drain (Id) @ 25°C:
- 15A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 10V
- Rds On (Max) @ Id, Vgs:
- 220mOhm @ 7.5A, 10V
- Vgs(th) (Max) @ Id:
- 5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 31 nC @ 10 V
- Vgs (Max):
- ±25V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1240 pF @ 100 V
- FET Feature:
- -
- Power Dissipation (Max):
- 110W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- TO-220
STP18N65M5 FAQ
1.How can I place an order for STP18N65M5 through Aetrix?
Please submit a Request for Quotation (RFQ) for STP18N65M5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STP18N65M5 reliable?
The price and inventory of STP18N65M5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STP18N65M5 is usually 5 days.
3.What payment methods are accepted for STP18N65M5?
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4.How is shipping managed for STP18N65M5?
STP18N65M5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STP18N65M5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STP18N65M5?
For technical support, including STP18N65M5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STP18N65M5 requirements.
6.How does Aetrix verify that STP18N65M5 is sourced from the original manufacturer or authorized distributors?
All STP18N65M5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STP18N65M5 meets industry standards.
7.What is the process for return or replacement of STP18N65M5?
All STP18N65M5 units undergo pre-shipment inspection (PSI). If there is an issue with STP18N65M5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STP18N65M5 part is unused and in its original packaging.
Return procedure for STP18N65M5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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