STMicroelectronics STP5N105K5

Overview

STP5N105K5 from STMicroelectronics is a 1050 V, 3.5 Ω (max), 3 A N-channel Power MOSFET in TO-220 package, built on MDmesh K5 vertical structure for ultra-low gate charge (12.5 nC) and high avalanche ruggedness (85 mJ). It serves as a high-voltage switching device in offline SMPS, PFC stages, and industrial HV DC-DC converters.

For engineers reviewing the STP5N105K5 datasheet, STP5N105K5 pinout, STP5N105K5 application, or STP5N105K5 equivalent, key selection criteria include its 1050 V breakdown voltage, 1.47 °C/W junction-to-case thermal resistance, 50 V/ns MOSFET dv/dt ruggedness, and Zener-protected gate-critical for reliable operation in high-dV/dt flyback and resonant topologies.

Technical Context

This MOSFET employs ST's proprietary MDmesh K5 technology, featuring a deep-trench vertical architecture that reduces specific on-resistance (R_DS(on) × area) and minimizes output capacitance (C_oss = 16 pF typ.) and reverse transfer capacitance (C_rss = 0.5 pF typ.). Its optimized charge profile enables fast switching with low E_oss (4 µJ at 800 V).

The device integrates a Zener-protected gate oxide and is 100% tested for single-pulse avalanche energy (E_AS = 85 mJ at T_J = 25 °C), supporting unclamped inductive switching in hard-switched converters. Its source-drain diode exhibits 400 ns reverse recovery time (T_J = 25 °C) and 2.3 µC Q_rr, enabling moderate-frequency quasi-resonant operation.

Key Specifications

Pinout & Package

TO-220 type A package with isolated tab (drain-connected); standard 3-pin through-hole mounting; tab electrically connected to drain for direct heatsink coupling and thermal path optimization.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage switching applications.

Compared with STP5N105K3 and IXTH5N100, STP5N105K5 delivers superior FoM (R_DS(on) × Q_g = 43.8 Ω·nC), verified avalanche margin, and gate-integrated protection-making it optimal for space-constrained, high-reliability 1000 V-class SMPS where thermal and voltage margin are non-negotiable.

Availability

STP5N105K5 is available at Aetrix Electronics and suitable for industrial AC-DC power supplies, high-voltage PFC boost stages, and resonant LLC converters requiring stable component supply and long-term manufacturability.

Supply support for STP5N105K5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, microcontrollers, and analog/mixed-signal ICs for industrial, automotive, and consumer markets.

STP5N105K5 belongs to the MDmesh K5 high-voltage Power MOSFET product line, engineered specifically for high-efficiency, high-density offline power conversion up to 3 kW with emphasis on avalanche robustness and thermal performance.

FAQ

What is the maximum continuous drain current at 100 °C case temperature?

The STP5N105K5 supports 2 A continuous drain current at T_C = 100 °C, as specified in Table 1 of DS10485 Rev 4. This derating reflects thermal limits of the TO-220 package and ensures safe operation within SOA boundaries under sustained high-temperature conditions.

Is the source-drain body diode suitable for freewheeling in hard-switched topologies?

Yes-the body diode is characterized with 400 ns t_rr and 2.3 µC Q_rr at T_J = 25 °C, making it usable for moderate-frequency freewheeling in CCM boost or flyback. However, its soft recovery is not optimized for ZVS, so synchronous rectification is preferred above 150 kHz.

Does STP5N105K5 require a negative gate turn-off voltage?

No-STP5N105K5 operates reliably with 0 V to +10 V gate drive. The gate threshold voltage (V_GS(th)) ranges from 3 to 5 V, and the device fully enhances at V_GS = 10 V. Negative gate bias is unnecessary and not recommended per ST's application guidance.

How does the 50 V/ns dv/dt ruggedness specification impact PCB layout?

This rating means the MOSFET can withstand 50 V/ns voltage transients across drain-source without spurious turn-on. Layout must minimize gate loop inductance (<10 nH) and use local gate resistors (≤10 Ω) to suppress ringing-critical for maintaining immunity in high-dV/dt environments like LLC primary switches.