Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

STMicroelectronics STU6N62K3

Name: STU6N62K3
Brand: STMicroelectronics
SKU: STU6N62K3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: STU6N62K3

Manufacturer:: STMicroelectronics

Category:: FETs, MOSFETs

Package:: TO-251-3 Short Leads, IPAK, TO-251AA

Datasheet:: STU6N62K3.pdf

Description:: MOSFET N-CH 620V 5.5A IPAK

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:14,990

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

STU6N62K3 from STMicroelectronics is an N-channel 620 V, 5.5 A MDmesh K3 Power MOSFET in IPAK (TO-251) package, featuring 0.95 Ω typ. R_DS(on), 140 mJ single-pulse avalanche energy, and 12 V/ns dv/dt capability. It serves as a high-voltage switching device in offline SMPS, PFC stages, and industrial motor drives where robustness under unclamped inductive switching is critical.

For engineers reviewing the STU6N62K3 datasheet, STU6N62K3 pinout, STU6N62K3 application, or STU6N62K3 equivalent, key selection criteria include its Zener-protected gate, low C_oss(er) (28 pF), improved diode reverse recovery (t_rr = 290 ns @ 25 °C), and 100% avalanche-tested reliability for high-reliability power conversion designs.

Technical Context

This MDmesh K3 MOSFET employs an optimized vertical structure to reduce specific on-resistance while maintaining high voltage blocking. Its low intrinsic capacitance (C_iss = 875 pF, C_oss = 100 pF) and fast switching (t_d(off) = 49 ns, t_f = 20 ns) enable high-frequency operation up to 100 kHz in hard-switched topologies.

The integrated Zener-protected gate withstands ±30 V stress, and its source-drain diode exhibits low V_SD (1.5 V @ 5.5 A) and controlled reverse recovery (Q_rr = 1.9 µC), reducing EMI and commutation losses in bridge configurations.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	620 V - Supports 400 V AC mains input with ≥20% safety margin in offline converters.
R_DS(on) max	1.2 Ω - Enables <5.5 A continuous conduction at T_C = 25 °C with ≤7.2 W conduction loss.
Q_g	34 nC - Determines gate drive power requirement; compatible with standard 1–2 A peak gate drivers.
E_AS	140 mJ - Guarantees single-pulse unclamped inductive switching survival without external snubbers.
t_rr	290 ns @ 25 °C - Limits diode commutation loss and reduces voltage overshoot during hard switching.
R_thJC	1.39 °C/W - Enables 90 W dissipation at T_C = 25 °C; requires heatsink for >30 W continuous operation.
dv/dt	12 V/ns - Resists false turn-on in high-noise environments like motor drives and industrial inverters.

Pinout & Package

IPAK (TO-251) package with isolated tab (drain-connected), 3-pin single-ended leadframe. Compact footprint (6.1 × 6.6 mm) and low-profile (16.5 mm height) suitable for space-constrained power modules and PCB-mounted heatsinks.

Pin/Terminal	Circuit Role	Design Meaning
TAB (Drain)	High-voltage drain connection and thermal path	Electrically tied to drain; must be isolated from chassis unless referenced to high-side potential.
Pin 1 (G)	Gate control terminal	Zener-protected; accepts ±30 V rating; requires <3.5 Ω series resistance for optimal ringing suppression.
Pin 3 (S)	Source reference and current return	Low-inductance source path essential for minimizing gate loop noise and ensuring stable switching.

Key Features

Feature	Design Value
100% avalanche tested	Each unit validated for 5.5 A repetitive avalanche current and 140 mJ single-pulse energy per DS5818.
Extremely high dv/dt capability	12 V/ns rated slope ensures immunity to parasitic turn-on in fast-switching half-bridge circuits.
Very low intrinsic capacitance	C_oss(er) = 28 pF enables reduced capacitive turn-off loss and higher efficiency at 65–100 kHz.
Improved diode reverse recovery	Q_rr = 1.9 µC and I_RRM = 13.5 A minimize shoot-through risk and EMI in synchronous rectification.
Zener-protected gate	Integrated gate-body Zener clamps transients to ±20 V, eliminating need for external gate protection diodes.

Applications

Industrial Motor Drives

Server PSU Primary Switch

Use Scenario: Half-bridge inverter stage for 750 W BLDC motor control in factory automation systems.

IC Role / Device Role / Timing Role: High-side switching element handling 400 V DC bus with 5.5 A RMS load current.

Use Value: Avalanche ruggedness prevents failure during motor stall events; low Q_g supports 80 kHz PWM without excessive gate drive loss.

Use Scenario: Active clamp forward or LLC resonant converter primary switch in 1 kW server power supply.

IC Role / Device Role / Timing Role: Main switching transistor operating at 100 kHz with 620 V blocking requirement.

Use Value: Low C_oss(er) reduces dead-time loss; fast t_r/t_f improves ZVS initiation margin in resonant topologies.

Telecom Rectifier Modules

EV Charger PFC Stage

Use Scenario: Boost PFC switch in 3 kW telecom rectifier operating from 90–264 V AC input.

IC Role / Device Role / Timing Role: Critical conduction mode (CRM) or continuous conduction mode (CCM) boost switch.

Use Value: Tight V_GS(th) tolerance (3.0–4.5 V) ensures consistent turn-on across temperature; low IDSS (<0.8 µA) minimizes standby leakage.

Use Scenario: 6.6 kW on-board charger front-end boost PFC stage with universal AC input.

IC Role / Device Role / Timing Role: High-voltage switching device in interleaved two-phase boost converter.

Use Value: Robust diode recovery (t_rr = 335 ns @ 150 °C) maintains efficiency at elevated junction temperatures during sustained charging.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage power switching applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
STP6N62K3	Same die, TO-220 package; R_thJC = 1.0 °C/W vs. 1.39 °C/W; no isolated tab.	Better thermal performance but larger footprint; unsuitable for surface-mount or tab-isolated layouts.	Select when board-level heatsinking is feasible and isolation of drain from chassis is not required.
IPP60R190C7	650 V CoolMOS™ C7; R_DS(on) = 0.19 Ω; higher Q_g (52 nC); no integrated Zener.	Lower conduction loss but higher gate drive demand; requires external gate protection.	Prefer for ultra-high-efficiency 65–135 kHz designs where gate drive capability and layout allow added protection components.

Compared with STP6N62K3, STU6N62K3 trades 0.39 °C/W higher thermal resistance for surface-mount compatibility and drain-tab isolation; versus IPP60R190C7, it offers lower gate charge and built-in Zener protection at the cost of higher R_DS(on), making it more suitable for cost-sensitive, thermally constrained, or transient-heavy industrial applications.

Availability

STU6N62K3 is available at Aetrix Electronics and suitable for industrial motor drives, telecom rectifiers, EV on-board chargers, and server PSUs requiring stable component supply, long-term lifecycle support, and traceable sourcing for production programs.

Supply support for STU6N62K3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for automotive, industrial, and consumer markets.

The MDmesh K3 product line targets high-voltage power conversion, delivering optimized R_DS(on)·Q_g figures and rugged avalanche performance for offline SMPS, PFC, and motor control applications demanding reliability under harsh electrical stress.

FAQ

Is STU6N62K3 suitable for use in zero-voltage switching (ZVS) topologies?

Yes. With C_oss(er) = 28 pF and low Q_gd/Q_gs ratio (22 nC / 4 nC), STU6N62K3 provides predictable resonant tank behavior and reliable ZVS initiation in LLC and phase-shifted full-bridge converters operating up to 300 kHz. Its 12 V/ns dv/dt rating further ensures gate stability during soft-switching transitions.

What is the maximum recommended gate resistor value for STU6N62K3 in a 100 kHz hard-switched application?

For 100 kHz operation with minimal switching loss and overshoot, a gate resistor of 4.7 Ω is validated in ST's test circuit (Figure 14). Values above 10 Ω increase t_d(off) and t_f, raising turn-off loss; below 2.2 Ω risks ringing due to low intrinsic gate resistance (3.5 Ω) and PCB inductance.

Does STU6N62K3 require external gate protection given its Zener-protected gate?

No external Zener is required for gate protection under normal operation. The integrated gate-body Zener clamps transients to ±20 V. However, a 10–22 Ω series resistor and 100 pF RC snubber at the gate-source remain recommended to suppress high-frequency oscillation induced by layout parasitics in high-dv/dt environments.

Can STU6N62K3 replace STF6N62K3 in existing designs?

Yes, with mechanical and thermal caveats. STF6N62K3 uses TO-220FP (isolated flange), while STU6N62K3 uses IPAK with drain-connected tab. Electrical specs are identical per DS5818 Rev 5. Replacement requires verifying PCB pad layout, heatsink isolation, and thermal interface design to accommodate the different package geometry and thermal path.

STU6N62K3 Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: SuperMESH3™

Package/Case:: TO-251-3 Short Leads, IPAK, TO-251AA

Packaging:: Tube

Product Status:: Active

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 620 V

Current - Continuous Drain (Id) @ 25°C:: 5.5A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 10V

Rds On (Max) @ Id, Vgs:: 1.2Ohm @ 2.8A, 10V

Vgs(th) (Max) @ Id:: 4.5V @ 50µA

Gate Charge (Qg) (Max) @ Vgs:: 30 nC @ 10 V

Vgs (Max):: ±30V

Input Capacitance (Ciss) (Max) @ Vds:: 875 pF @ 50 V

FET Feature:: -

Power Dissipation (Max):: 90W (Tc)

Operating Temperature:: 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: TO-251 (IPAK)

STU6N62K3 FAQ

1.How can I place an order for STU6N62K3 through Aetrix?

Please submit a Request for Quotation (RFQ) for STU6N62K3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for STU6N62K3 reliable?

The price and inventory of STU6N62K3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STU6N62K3 is usually 5 days.

3.What payment methods are accepted for STU6N62K3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STU6N62K3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for STU6N62K3?

STU6N62K3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your STU6N62K3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for STU6N62K3?

For technical support, including STU6N62K3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STU6N62K3 requirements.

6.How does Aetrix verify that STU6N62K3 is sourced from the original manufacturer or authorized distributors?

All STU6N62K3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STU6N62K3 meets industry standards.

7.What is the process for return or replacement of STU6N62K3?

All STU6N62K3 units undergo pre-shipment inspection (PSI). If there is an issue with STU6N62K3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The STU6N62K3 part is unused and in its original packaging.

Return procedure for STU6N62K3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…