STMicroelectronics STU7N105K5

Overview

STU7N105K5 from STMicroelectronics is a 1050 V, 4 A N-channel high-voltage Power MOSFET in IPAK (TO-251) package, fabricated with MDmesh K5 vertical structure technology. It delivers 1.4 Ω typical R_DS(on), 11 nC total gate charge, and 100% avalanche-tested ruggedness for high-efficiency switching in offline SMPS, PFC stages, and industrial HV DC-DC converters.

For engineers reviewing the STU7N105K5 datasheet, STU7N105K5 pinout, STU7N105K5 application, or STU7N105K5 equivalent, this device offers verified ultra-low Q_g/R_DS(on) FoM, Zener-protected gate, and 50 V/ns MOSFET dv/dt ruggedness - critical for reliable operation in hard-switched 800 V bus systems.

Technical Context

This MOSFET employs ST's proprietary MDmesh K5 vertical superjunction architecture to minimize conduction and switching losses simultaneously. Its 1.14 °C/W R_thJC and 100 V/ns diode recovery dv/dt capability enable compact heatsink designs in high-power density topologies.

The device integrates a built-in gate Zener clamp (±30 V V_GS rating), supports 16 A pulsed drain current, and features 132 mJ single-pulse avalanche energy at T_J = 25 °C - confirming robust unclamped inductive switching performance per JEDEC JESD24-11.

Key Specifications

Pinout & Package

IPAK (TO-251) package with isolated tab (Drain-connected), 3-pin single-ended leadframe. Compact 6.1 × 6.6 × 16.5 mm outline optimized for manual and automated through-hole assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage switching applications.

Compared with STP7N105K5 and IXTH7N100L2, STU7N105K5 delivers superior power density (1.14 °C/W vs 1.25/1.5 °C/W), lowest FoM (R_DS(on) × Q_g = 22 Ω·nC), and guaranteed avalanche ruggedness - making it optimal for space-constrained, high-reliability 800 V systems.

Availability

STU7N105K5 is available at Aetrix Electronics and suitable for industrial AC-DC power supplies, telecom PFC circuits, and EV charging station DC-DC stages requiring stable component supply and long-term lifecycle assurance.

Supply support for STU7N105K5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for industrial, automotive, and consumer markets.

This device belongs to ST's MDmesh K5 high-voltage Power MOSFET product line, engineered specifically for high-efficiency, high-power-density switching applications in 700–1000 V DC-link systems.

FAQ

What is the maximum recommended gate resistor value for STU7N105K5 in a 100 kHz PFC application?

A 4.7 Ω gate resistor is validated in ST's reference test circuit (Figure 14, DS10290) for 100 kHz operation, yielding 17.5 ns t_d(on) and 43 ns t_d(off). Values above 10 Ω increase switching losses disproportionately due to 11 nC Q_g; below 2.2 Ω risks gate driver overstress during 50 V/ns dv/dt events.

Does STU7N105K5 require external gate protection given its Zener-protected structure?

No external Zener is needed: the integrated gate-body Zener clamps V_GS to ±30 V. However, a 10–22 Ω series gate resistor and 100 pF RC snubber between gate and source are recommended to suppress ringing induced by 50 V/ns dv/dt and 7 Ω intrinsic R_g.

Can STU7N105K5 replace STW7N105K5 in existing designs?

No - STW7N105K5 uses TO-247 package with different thermal and mechanical interface. While electrically identical, STU7N105K5's IPAK tab requires revised PCB layout, heatsink mounting, and creepage/clearance verification per IEC 62368-1 for 1050 V systems.

What is the safe operating area (SOA) limitation at T_C = 100 °C?

At T_C = 100 °C, continuous drain current is derated to 3 A (Table 1). The SOA curve (Figure 1) shows pulse-limited operation up to 16 A for ≤100 µs at V_DS ≤ 525 V, constrained by R_DS(on) and thermal mass - not avalanche or secondary breakdown.