STMicroelectronics STW65N023M9-4

Overview

STW65N023M9-4 from STMicroelectronics is a 650 V, 92 A N-channel super-junction Power MOSFET in TO247-4 package, featuring 23.0 mΩ max R_DS(on), 230 nC total gate charge, and 120 V/ns dv/dt ruggedness. It integrates an extra driving source pin for enhanced switching control and is 100% avalanche tested for robustness in high-efficiency SMPS, PFC, and industrial inverters.

For engineers reviewing the STW65N023M9-4 datasheet, STW65N023M9-4 pinout, STW65N023M9-4 application, or STW65N023M9-4 equivalent, key selection criteria include its low R_DS(on)·Q_g figure-of-merit (5.29 Ω·nC), high diode recovery dv/dt capability (50 V/ns), and dedicated driver source terminal enabling precise gate loop optimization.

Technical Context

This MDmesh M9 silicon MOSFET employs a multi-drain manufacturing process to achieve ultra-low on-resistance density and reduced output capacitance (C_oss = 140 pF). Its structure delivers superior power density versus prior-generation super-junction devices while maintaining stable threshold voltage (3.2–4.2 V) across –55 °C to 150 °C.

The TO247-4 package includes separate driver source (pin 3) and power source (pin 2) terminals to minimize source inductance in the gate drive path, directly supporting fast, low-overshoot switching with 45 ns turn-on delay and 7 ns fall time under 4.7 Ω gate resistance.

Key Specifications

Pinout & Package

TO247-4 package with isolated tab (Drain), four leads: Pin 1 (Drain/TAB), Pin 2 (Power Source), Pin 3 (Driver Source), Pin 4 (Gate). The dual-source configuration separates high-current power return from low-noise gate drive return to suppress common-source inductance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage power switching applications.

Compared with IXTH60N65X2 and SPW47N60C3, STW65N023M9-4 delivers the lowest R_DS(on)·Q_g product and unique driver-source isolation-making it optimal for new high-efficiency, high-power-density designs where layout-controlled switching performance is critical.

Availability

STW65N023M9-4 is available at Aetrix Electronics and suitable for server power supplies, solar inverters, industrial motor drives, and EV on-board chargers requiring stable component supply and long-term production continuity.

Supply support for STW65N023M9-4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal integrated circuits for automotive, industrial, and power applications.

This device belongs to the MDmesh M9 super-junction MOSFET product line, engineered specifically for high-efficiency, medium-to-high-voltage switching in industrial SMPS, renewable energy inverters, and motor control systems.

FAQ

What is the purpose of the separate driver source (pin 3) and power source (pin 2) terminals?

The driver source pin provides a dedicated low-inductance return path exclusively for the gate driver circuit, isolating it from high-di/dt power source current. This separation minimizes common-source inductance, preventing gate voltage undershoot/overshoot and enabling stable 100+ kHz switching without external gate resistors exceeding 10 Ω.

Is STW65N023M9-4 suitable for synchronous rectification applications?

No - this is an N-channel enhancement-mode MOSFET optimized for high-side or half-bridge switching, not synchronous rectification. Its body diode reverse recovery characteristics (Q_rr = 5.45 µC at 25 °C) are not optimized for low-loss freewheeling; dedicated SR controllers or logic-level MOSFETs with faster diodes are recommended for that function.

What thermal derating applies above 25 °C case temperature?

At T_C = 100 °C, continuous drain current drops to 58 A (from 92 A at 25 °C), reflecting linear derating governed by R_thJC = 0.27 °C/W and maximum junction temperature of 150 °C. Power dissipation must be limited to 292 W at 100 °C case to maintain safe operating area compliance.

Does the 100 % avalanche test cover both repetitive and single-pulse conditions?

Yes - each unit undergoes 100 % production testing for single-pulse avalanche energy (E_AS = 1307 mJ at V_DD = 50 V) and repetitive avalanche stress (I_AR = 12 A, pulse width limited by T_J max). Test conditions follow JEDEC JESD24-11 and are documented in DS14037 Rev 4, Section 3.