STMicroelectronics STW7N105K5

Overview

STW7N105K5 from STMicroelectronics is a 1050 V, 4 A N-channel power MOSFET in IPAK (TO-251) package, fabricated with MDmesh K5 vertical structure technology. It delivers 1.4 Ω typical R_DS(on), 11 nC total gate charge, and 100% avalanche-tested ruggedness for high-voltage switching in industrial SMPS and PFC stages.

For engineers reviewing the STW7N105K5 datasheet, STW7N105K5 pinout, STW7N105K5 application, or STW7N105K5 equivalent, key selection criteria include its ultra-low Q_g/R_DS(on) figure of merit, 50 V/ns MOSFET dv/dt ruggedness, Zener-protected gate, and 132 mJ single-pulse avalanche energy at 25 °C.

Technical Context

This device employs ST's MDmesh K5 proprietary vertical superjunction architecture to achieve industry-leading R_DS(on) × area and FoM. Its 1.14 °C/W junction-to-case thermal resistance supports high-power density designs in constrained thermal environments.

The MOSFET integrates a built-in gate Zener clamp and is fully characterized for unclamped inductive switching (UIS), with verified 1.5 A repetitive avalanche current and 600 ns reverse recovery time at 150 °C - enabling robust operation in hard-switched converters.

Key Specifications

Pinout & Package

STW7N105K5 is housed in an IPAK (TO-251) package with exposed drain tab for enhanced thermal dissipation. The 3-pin configuration features a single large metal tab (Drain) on the backside and three leads on the front edge.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage power switching applications.

Compared with STP7N105K5 and IXTH7N100D2, STW7N105K5 provides superior power density via IPAK thermal performance, best-in-class FoM, and built-in gate protection - making it optimal for space-constrained, high-reliability industrial converters.

Availability

STW7N105K5 is available at Aetrix Electronics and suitable for industrial switch-mode power supplies, active PFC circuits, and high-voltage DC-DC converters requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for STW7N105K5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, microcontrollers, sensors, and automotive ICs.

STW7N105K5 belongs to the MDmesh K5 high-voltage power MOSFET product line, engineered specifically for efficiency-critical industrial power conversion where high breakdown voltage, low conduction loss, and avalanche ruggedness are mandatory.

FAQ

What is the maximum continuous drain current for STW7N105K5 at 100 °C case temperature?

The maximum continuous drain current is 3 A at T_C = 100 °C, as specified in Table 1 of DS10290 Rev 3. This derating reflects thermal limitations of the IPAK package and ensures safe operation within the SOA boundary at elevated temperatures.

Does STW7N105K5 include integrated gate protection?

Yes - STW7N105K5 features an integrated gate-source Zener diode with ±20 V clamping, confirmed in the "Gate body leakage current" specification (I_GSS = ±10 µA at V_GS = ±20 V) and explicitly stated in the Features section of the datasheet.

Can STW7N105K5 replace STU7N105K5 in existing designs?

No - STU7N105K5 uses IPAK package with G(1)-D(2)-S(3) pinout, while STW7N105K5 is also IPAK but has identical pinout per AM01476v1_tab. However, STW7N105K5 is a distinct orderable part with separate datasheet (DS10290 Rev 3) and updated test conditions; direct substitution requires validation of gate drive timing and thermal interface.

What is the typical reverse recovery charge (Q_rr) of the body diode at 150 °C?

The typical reverse recovery charge is 4.4 µC at T_J = 150 °C, as measured under ISD = 4 A, di/dt = 100 A/µs, and V_DD = 60 V (Table 7, second Q_rr entry). This value is critical for estimating commutation losses in synchronous rectification or bidirectional topologies.