Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

STMicroelectronics STY140NS10

Name: STY140NS10
Brand: STMicroelectronics
SKU: STY140NS10
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: STY140NS10

Manufacturer:: STMicroelectronics

Category:: FETs, MOSFETs

Package:: TO-247-3

Datasheet:: STY140NS10.pdf

Description:: MOSFET N-CH 100V 140A MAX247

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,186

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

STY140NS10 from STMicroelectronics is an N-channel enhancement-mode power MOSFET designed for high-current, high-speed switching in primary-side SMPS stages. It delivers 140 A continuous drain current at T_C = 25°C, R_DS(on) ≤ 0.011 Ω at V_GS = 10 V, and 100 V V_DSS, with full 2900 mJ single-pulse avalanche energy rating.

For engineers reviewing the STY140NS10 datasheet, STY140NS10 pinout, STY140NS10 application, or STY140NS10 equivalent, key selection factors include its Max247™ package thermal performance (R_thj-case = 0.33 °C/W), gate charge profile (Q_g = 450 nC typ.), and diode recovery robustness (trr = 275 ns, I_RRM = 15 A).

Technical Context

This device employs ST's proprietary MESH OVERLAY™ process with strip layout and edge termination to achieve industry-leading R_DS(on)/area and dv/dt immunity (5 V/ns). Its standard threshold (V_GS(th) = 2–4 V) enables direct drive from 10 V gate drivers without level-shifting.

The integrated body diode supports synchronous rectification and hard-switched flyback/LLC topologies, with characterized reverse recovery (Q_rr = 2 µC, trr = 275 ns) and rated source-drain current (I_SD = 140 A) under zero-gate-bias conditions.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DSS	100 V - Supports 48 V input bus designs with ≥2× safety margin against transient overvoltage.
R_DS(on) max	0.011 Ω - Enables <1.5 W conduction loss at 140 A, critical for high-efficiency 1 kW+ SMPS.
I_D cont @ T_C=25°C	140 A - Sustains full-load current in TO-247-3L-based power stages without forced air.
E_AS	2900 mJ - Withstands repetitive inductive turn-off stress in unclamped inductive switching (UIS) applications.
Q_g	450 nC - Determines gate driver power requirement; compatible with 1–2 A peak gate drivers at 100 kHz switching.
trr	275 ns - Limits diode reverse recovery losses in hard-switched converters operating up to 200 kHz.
R_thj-case	0.33 °C/W - Enables junction temperature rise of only 148°C at 450 W dissipation, supporting compact heatsink design.

Pinout & Package

STY140NS10 uses the Max247™ variant of the TO-247-3L package: isolated tab (drain), three leads-Gate (pin 1), Drain (pin 2), Source (pin 3)-with mechanical dimensions per ST's P025Q drawing (D = 20.0 mm, E = 15.6 mm, L = 14.7 mm).

Pin/Terminal	Circuit Role	Design Meaning
Pin 1 (G)	Gate terminal	Controls channel conduction; requires ≤±20 V drive; Q_gs = 70 nC ensures fast turn-on with low Miller plateau duration.
Pin 2 (D)	Drain terminal / heat sink interface	High-voltage node (100 V rating); electrically isolated tab allows mounting to heatsink without insulator.
Pin 3 (S)	Source terminal / reference node	Common return for gate drive and load current; low-inductance layout essential to minimize switching overshoot.

Key Features

Feature	Design Value
MESH OVERLAY™ process	Delivers lowest R_DS(on)/die area among 100 V MOSFETs, reducing die size and cost while maintaining SOA.
100% avalanche tested	Each unit validated to 2900 mJ UIS stress, eliminating field failure risk in unclamped inductive loads.
Standard threshold (2–4 V)	Enables direct interfacing with industry-standard 10 V PWM controllers (e.g., UC384x, TL494) without gate bias circuitry.
dv/dt immunity	Rated 5 V/ns - suppresses false turn-on during high dV/dt commutation, critical in half-bridge and phase-shifted topologies.

Applications

Server PSU Primary Switch

Industrial UPS Inverter Stage

Use Scenario: High-density 3 kW server power supply operating at 100–200 kHz with active clamp forward topology.

IC Role / Device Role / Timing Role: Primary-side main switch handling 140 A peak current during 50% duty cycle at 100 V bus.

Use Value: Low R_DS(on) (0.011 Ω) reduces conduction loss to <220 W, enabling >95% efficiency at full load without liquid cooling.

Use Scenario: 10 kVA industrial uninterruptible power supply using full-bridge inverter with 48 V DC input.

IC Role / Device Role / Timing Role: High-side switching element in bridge leg, switching at 16 kHz with 100% duty-cycle capability during battery boost mode.

Use Value: 2900 mJ avalanche rating prevents failure during output short-circuit events, meeting IEC 62040-1 fault tolerance requirements.

Solar Microinverter DC-DC Stage

EV Onboard Charger PFC Boost

Use Scenario: 300 W microinverter with interleaved boost converter feeding 400 V DC link from 30–60 V PV input.

IC Role / Device Role / Timing Role: Synchronous rectifier in secondary-side LLC resonant stage, conducting 140 A pulsed current at 300–500 kHz.

Use Value: Fast diode recovery (trr = 275 ns) minimizes reverse recovery loss, improving light-load efficiency by 1.2% versus legacy 100 V MOSFETs.

Use Scenario: 6.6 kW bidirectional OBC with two-phase interleaved PFC operating at 65 kHz.

IC Role / Device Role / Timing Role: Boost switch in high-current phase leg, sustaining 140 A RMS current with 100 V blocking capability.

Use Value: R_thj-case = 0.33 °C/W allows 110°C case temperature at full load, enabling compact aluminum heatsink integration within automotive form factor.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current 100 V power MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IXFH140N10P	R_DS(on) = 0.0095 Ω (typ), Q_g = 480 nC, R_thj-case = 0.35 °C/W	Higher gate charge increases driver loss; identical avalanche rating (2900 mJ)	Preferred when lower R_DS(on) outweighs gate drive overhead in <100 kHz designs.
IRFP4110PBF	R_DS(on) = 0.012 Ω (max), Q_g = 390 nC, E_AS = 2100 mJ	Lower avalanche energy limits use in unclamped inductive circuits; faster switching due to lower Q_g	Selected where reduced gate drive power is prioritized over ruggedness in well-clamped topologies.

Compared with IXFH140N10P and IRFP4110PBF, STY140NS10 offers optimal balance of low R_DS(on), moderate Q_g, and highest avalanche robustness-making it preferred for mission-critical 100 V SMPS where reliability under transient stress is non-negotiable.

Availability

STY140NS10 is available at Aetrix Electronics and suitable for server power supplies, industrial UPS inverters, solar microinverters, and EV onboard chargers requiring stable component supply across multi-year production cycles.

Supply support for STY140NS10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing analog, MCU, power, and sensor solutions for industrial, automotive, and consumer markets.

The Max247™ power MOSFET product line targets high-efficiency, high-reliability switched-mode power conversion, emphasizing ruggedness, thermal efficiency, and manufacturability in high-volume power electronics.

FAQ

Is STY140NS10 suitable for synchronous rectification?

Yes. Its low R_DS(on) (0.011 Ω) and characterized body diode (V_SD = 1.5 V at 140 A, trr = 275 ns) support efficient synchronous rectification in LLC and resonant converters. Gate drive must be precisely timed to avoid shoot-through, and layout must minimize source inductance to ensure clean turn-off.

What is the maximum recommended gate resistor for 100 kHz operation?

A 4.7 Ω gate resistor is validated in ST's test circuit (Figure 1) for 100 kHz switching with 70 A load. For 140 A operation, reduce to 2.2–3.3 Ω to maintain td(on)/td(off) ≤ 500 ns and limit peak gate current to <3 A, avoiding driver saturation and excessive switching loss.

Does STY140NS10 require a thermal pad or insulator when mounted to a heatsink?

No. The Max247™ TO-247-3L package features an electrically isolated drain tab. Direct mounting to an un-insulated heatsink is permitted, simplifying thermal design and reducing thermal resistance by ~0.1–0.2 °C/W versus insulated mounting methods.

Can STY140NS10 replace IRFP460 in existing 500 W SMPS designs?

Yes, with validation. STY140NS10 offers lower R_DS(on) (0.011 Ω vs. 0.27 Ω), higher ID (140 A vs. 20 A), and superior avalanche rating. Layout changes may be needed due to larger die size and different pinout (G-D-S vs. G-D-S orientation matches), but gate drive compatibility is maintained with 10 V logic-level control.

STY140NS10 Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: MESH OVERLAY™

Package/Case:: TO-247-3

Packaging:: Tube

Product Status:: Obsolete

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 100 V

Current - Continuous Drain (Id) @ 25°C:: 140A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 10V

Rds On (Max) @ Id, Vgs:: 11mOhm @ 70A, 10V

Vgs(th) (Max) @ Id:: 4V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 600 nC @ 10 V

Vgs (Max):: ±20V

Input Capacitance (Ciss) (Max) @ Vds:: 12600 pF @ 25 V

FET Feature:: -

Power Dissipation (Max):: 450W (Tc)

Operating Temperature:: -55°C ~ 175°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: MAX247™

STY140NS10 FAQ

1.How can I place an order for STY140NS10 through Aetrix?

Please submit a Request for Quotation (RFQ) for STY140NS10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for STY140NS10 reliable?

The price and inventory of STY140NS10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STY140NS10 is usually 5 days.

3.What payment methods are accepted for STY140NS10?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STY140NS10 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for STY140NS10?

STY140NS10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your STY140NS10 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for STY140NS10?

For technical support, including STY140NS10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STY140NS10 requirements.

6.How does Aetrix verify that STY140NS10 is sourced from the original manufacturer or authorized distributors?

All STY140NS10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STY140NS10 meets industry standards.

7.What is the process for return or replacement of STY140NS10?

All STY140NS10 units undergo pre-shipment inspection (PSI). If there is an issue with STY140NS10, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The STY140NS10 part is unused and in its original packaging.

Return procedure for STY140NS10:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…