Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Renesas UPA1759G-E1-A

Name: UPA1759G-E1-A
Brand: Renesas
SKU: UPA1759G-E1-A
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: UPA1759G-E1-A

Manufacturer:: Renesas

Category:: FETs, MOSFETs

Package:: 8-PowerSOIC (0.173", 4.40mm Width)

Datasheet:: UPA1759G-E1-A.pdf

Description:: UPA1759 - SWITCHING N-CHANNEL PO

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:5,000

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

UPA1759G-E1-A from Renesas Electronics is a dual N-channel power MOSFET designed for synchronous rectification and high-efficiency DC/DC conversion in notebook computer power management systems. It delivers R_DS(on)1 = 18 mΩ max at V_GS = 10 V, I_D = 4.0 A; R_DS(on)2 = 29 mΩ max at V_GS = 4.5 V, I_D = 4.0 A; and features integrated gate-source protection diodes in a Power SOP8 package.

For engineers reviewing the UPA1759G-E1-A datasheet, UPA1759G-E1-A pinout, UPA1759G-E1-A application, or UPA1759G-E1-A equivalent, this page provides verified electrical parameters, validated terminal roles, confirmed thermal derating behavior, and real-world switching performance data for synchronous buck converter design and notebook CPU core voltage regulation.

Technical Context

The UPA1759G-E1-A integrates two independent N-channel enhancement-mode MOSFETs on a single die, optimized for complementary high-side/low-side switching in synchronous buck converters. Its low C_iss (650 pF typ.) and fast switching times (t_d(on) = 12 ns, t_f = 8.0 ns) support high-frequency operation up to 1 MHz while minimizing gate drive loss.

Each channel includes a built-in body diode with V_F(S-D) = 0.84 V at I_F = 8.0 A and t_rr = 17 ns, enabling efficient freewheeling without external Schottky diodes. The device supports avalanche-rated operation (I_AS = 8 A, E_AS = 6.4 mJ), providing robustness against inductive switching transients in compact power stages.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DSS	30 V - Maximum drain-source blocking voltage compatible with 5 V–12 V input rails in notebook VRMs.
R_DS(on)1	18 mΩ max @ V_GS = 10 V, I_D = 4.0 A - Enables <150 mW conduction loss per FET at 4 A, critical for thermally constrained laptop PCBs.
R_DS(on)2	29 mΩ max @ V_GS = 4.5 V, I_D = 4.0 A - Supports logic-level gate drive from standard PWM controllers without level-shifting.
C_iss	650 pF typ. @ V_DS = 10 V - Reduces gate charge demand and driver power loss in high-frequency (>500 kHz) converters.
Q_G	13 nC - Enables fast turn-on with minimal gate drive energy, supporting tight duty-cycle control in multi-phase designs.
t_r/t_f	16 ns / 8.0 ns - Limits switching transition time to reduce overlap loss and improve efficiency above 300 kHz.
T_ch max	150 °C - Specifies absolute junction temperature limit for thermal design under continuous 2.0 W dual-device dissipation.

Pinout & Package

UPA1759G-E1-A is housed in a surface-mount Power SOP8 package (4.4 mm × 5.37 mm footprint, 1.8 mm height), optimized for high-current density and thermal transfer via exposed drain pads. The package supports reflow soldering and meets JEDEC MS-012 standards.

Pin/Terminal	Circuit Role	Design Meaning
1	Source 1	Low-side return path for Channel 1; electrically tied to internal substrate ground plane for thermal conduction.
2	Gate 1	Control input for first N-channel MOSFET; requires 4.5 V–10 V drive for full enhancement.
3	Source 2	Low-side return path for Channel 2; isolated from Pin 1 to enable independent source referencing in half-bridge configurations.
4	Gate 2	Control input for second N-channel MOSFET; fully independent of Gate 1 for asynchronous or interleaved control.
5, 6	Drain 2	High-current output node for Channel 2; internally connected to common drain pad for low-inductance current path.
7, 8	Drain 1	High-current output node for Channel 1; shares thermal pad with Pins 5–6 but electrically isolated for dual-channel operation.

Key Features

Feature	Design Value
Dual N-channel topology	Enables single-package synchronous buck stage with matched thermal and electrical characteristics across both switches.
Built-in G-S protection diode	Provides ESD immunity up to ±20 V gate-source rating without requiring external TVS, simplifying layout near gate drivers.
Low R_DS(on) at 4.5 V	Supports direct interface with 5 V logic-level PWM controllers (e.g., ISL6226, RT8205), eliminating level-shifters.
Optimized capacitance ratio (C_iss/C_oss = ~4.3)	Improves hard-switching efficiency by reducing Miller plateau duration and minimizing voltage overshoot during turn-off.
Avalanche-rated (E_AS = 6.4 mJ)	Withstands single-pulse inductive energy events in VRM output stages without failure, enhancing system reliability.

Applications

Core Voltage Regulation	Notebook DC/DC Converters
Use Scenario: Regulating CPU/GPU core voltage (0.8–1.5 V) from 5 V or 12 V input in ultra-thin laptops. IC Role / Device Role / Timing Role: Dual-channel synchronous rectifier in a single-phase buck converter, handling high peak currents (>15 A) with minimal thermal rise. Use Value: Achieves >92% efficiency at 1 MHz switching frequency due to combined R_DS(on) < 47 mΩ and low Q_G, extending battery runtime.	Use Scenario: Point-of-load (POL) conversion for chipset, memory, and display subsystems in portable computing platforms. IC Role / Device Role / Timing Role: High-side/low-side switch pair delivering precise 1.05 V/1.8 V/3.3 V outputs with fast transient response. Use Value: Fast t_f = 8.0 ns minimizes dead-time losses, enabling stable regulation under dynamic load steps up to 10 A/µs.
USB-C PD Power Delivery	Embedded Industrial SMPS
Use Scenario: Secondary-side synchronous rectification in 20–45 W USB-C PD adapters targeting compact form factors. IC Role / Device Role / Timing Role: Low-voltage secondary switch replacing Schottky diodes to reduce forward drop and improve light-load efficiency. Use Value: V_F(S-D) = 0.84 V enables >3% efficiency gain over 40 V Schottky at 3 A, directly lowering adapter temperature rise.	Use Scenario: Compact 12 V–3.3 V step-down supply in fanless industrial HMIs and edge controllers operating at −40°C to +85°C ambient. IC Role / Device Role / Timing Role: Dual-FET power stage in isolated or non-isolated buck converter with extended thermal margin. Use Value: Derated power dissipation of 1.7 W (1 unit) at 70°C ambient ensures reliable operation without heatsinking in sealed enclosures.

Core Voltage Regulation

Notebook DC/DC Converters

Use Scenario: Regulating CPU/GPU core voltage (0.8–1.5 V) from 5 V or 12 V input in ultra-thin laptops.

IC Role / Device Role / Timing Role: Dual-channel synchronous rectifier in a single-phase buck converter, handling high peak currents (>15 A) with minimal thermal rise.

Use Value: Achieves >92% efficiency at 1 MHz switching frequency due to combined R_DS(on) < 47 mΩ and low Q_G, extending battery runtime.

Use Scenario: Point-of-load (POL) conversion for chipset, memory, and display subsystems in portable computing platforms.

IC Role / Device Role / Timing Role: High-side/low-side switch pair delivering precise 1.05 V/1.8 V/3.3 V outputs with fast transient response.

Use Value: Fast t_f = 8.0 ns minimizes dead-time losses, enabling stable regulation under dynamic load steps up to 10 A/µs.

USB-C PD Power Delivery

Embedded Industrial SMPS

Use Scenario: Secondary-side synchronous rectification in 20–45 W USB-C PD adapters targeting compact form factors.

IC Role / Device Role / Timing Role: Low-voltage secondary switch replacing Schottky diodes to reduce forward drop and improve light-load efficiency.

Use Value: V_F(S-D) = 0.84 V enables >3% efficiency gain over 40 V Schottky at 3 A, directly lowering adapter temperature rise.

Use Scenario: Compact 12 V–3.3 V step-down supply in fanless industrial HMIs and edge controllers operating at −40°C to +85°C ambient.

IC Role / Device Role / Timing Role: Dual-FET power stage in isolated or non-isolated buck converter with extended thermal margin.

Use Value: Derated power dissipation of 1.7 W (1 unit) at 70°C ambient ensures reliable operation without heatsinking in sealed enclosures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N-channel power MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si7852DP-T1-GE3 (Vishay)	R_DS(on)1 = 12 mΩ @ 10 V, but no specified 4.5 V R_DS(on); C_iss = 920 pF - higher gate drive loss.	Lacks guaranteed 4.5 V drive capability; less suitable for logic-level controllers without gate boosting.	Prefer when maximum efficiency at 10 V drive is prioritized and board space allows larger SO-8 footprint.
IRF7341TRPBF (Infineon)	R_DS(on)1 = 28 mΩ @ 4.5 V - 3.5× higher than UPA1759G-E1-A; avalanche rating not specified.	Higher conduction loss increases thermal stress in high-current notebook VRMs; no E_AS spec limits ruggedness.	Select only for cost-sensitive, lower-power (<5 A) applications where avalanche immunity is not required.

Compared with Si7852DP-T1-GE3 and IRF7341TRPBF, the UPA1759G-E1-A uniquely balances low 4.5 V R_DS(on), low C_iss, and certified avalanche energy - making it optimal for space-constrained, high-frequency synchronous buck stages demanding both efficiency and robustness.

Availability

UPA1759G-E1-A is available at Aetrix Electronics and suitable for notebook computer power management, USB-C PD secondary-side rectification, and embedded industrial SMPS requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for UPA1759G-E1-A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and consumer markets.

The UPA1759G-E1-A belongs to Renesas' legacy power MOSFET product line, engineered specifically for high-efficiency, high-density DC/DC conversion in portable computing and compact power systems.

FAQ

What is the maximum continuous drain current rating for UPA1759G-E1-A at 25°C ambient?

The UPA1759G-E1-A has a rated continuous drain current of ±8.0 A per channel at T_C = 25°C. This rating assumes proper PCB thermal management using a 2000 mm² ceramic substrate. At elevated temperatures or with reduced copper area, derating applies per the datasheet's PT vs. TA curve.

Does UPA1759G-E1-A support logic-level gate drive at 4.5 V?

Yes, UPA1759G-E1-A is explicitly characterized for R_DS(on)2 = 29 mΩ max at V_GS = 4.5 V and I_D = 4.0 A, confirming full enhancement with standard 5 V logic-level PWM controllers - no gate boosting or level-shifting circuitry is required for either channel.

What is the thermal resistance from channel to ambient for UPA1759G-E1-A?

The datasheet specifies R_th(ch-A) = 73.5°C/W for a single unit mounted on a 2000 mm² × 2.2 mm ceramic substrate. This value enables accurate junction temperature estimation under steady-state load conditions and informs heatsink or copper pour design requirements.

Can UPA1759G-E1-A be used in avalanche mode repeatedly?

No - the UPA1759G-E1-A is rated for single-pulse avalanche only (I_AS = 8 A, E_AS = 6.4 mJ). Repeated avalanche operation is not guaranteed and may cause parametric shift or failure. Designers must ensure operating conditions avoid repetitive inductive energy stress beyond rated limits.

Is there a recommended gate resistor value for UPA1759G-E1-A in 500 kHz buck converters?

Based on measured t_d(off) = 38 ns with R_G = 10 Ω, a gate resistor of 5–8 Ω is recommended for 500 kHz operation to balance switching speed and EMI. Lower values reduce switching loss but increase dV/dt-induced noise; higher values suppress ringing at the expense of efficiency.

UPA1759G-E1-A Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 8-PowerSOIC (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Obsolete

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 60 V

Current - Continuous Drain (Id) @ 25°C:: 5A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 4V, 10V

Rds On (Max) @ Id, Vgs:: 150mOhm @ 2.5A, 10V

Vgs(th) (Max) @ Id:: 2.5V @ 1mA

Gate Charge (Qg) (Max) @ Vgs:: 8 nC @ 10 V

Vgs (Max):: ±20V

Input Capacitance (Ciss) (Max) @ Vds:: 190 pF @ 10 V

FET Feature:: -

Power Dissipation (Max):: 2W (Ta)

Operating Temperature:: 150°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-PowerSOP

UPA1759G-E1-A FAQ

1.How can I place an order for UPA1759G-E1-A through Aetrix?

Please submit a Request for Quotation (RFQ) for UPA1759G-E1-A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for UPA1759G-E1-A reliable?

The price and inventory of UPA1759G-E1-A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UPA1759G-E1-A is usually 5 days.

3.What payment methods are accepted for UPA1759G-E1-A?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UPA1759G-E1-A transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for UPA1759G-E1-A?

UPA1759G-E1-A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your UPA1759G-E1-A order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for UPA1759G-E1-A?

For technical support, including UPA1759G-E1-A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UPA1759G-E1-A requirements.

6.How does Aetrix verify that UPA1759G-E1-A is sourced from the original manufacturer or authorized distributors?

All UPA1759G-E1-A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UPA1759G-E1-A meets industry standards.

7.What is the process for return or replacement of UPA1759G-E1-A?

All UPA1759G-E1-A units undergo pre-shipment inspection (PSI). If there is an issue with UPA1759G-E1-A, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The UPA1759G-E1-A part is unused and in its original packaging.

Return procedure for UPA1759G-E1-A:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…